SelectLink(TM) Verilog Source Code Generator For Virtex/Virtex-E FPGAs

 
The SelectLink(TM) resource is a high-speed inter-chip data channel for Virtex FPGAs. Systems that include two or more FPGAs often require high-bandwidth data paths between devices. As the clock period and switching times of digital circuits become shorter, straightforward methods of transferring data between devices are often inadequate. At high frequencies, signal propagation delay and reflections that occur in conductors just a few centimeters long must be taken into account. The SelectLink communications channel utilizes special features of the Virtex family, including Delay Locked Loops, Block SelectRAM, and SelectI/O technology, to create a system that can move large amounts of data between FPGAs at very high speeds. The SelectLink tool allows logic designers everywhere to instantly create customized SelectLink Verilog source code. The modules are easily instantiated in the designers top level code for a complete system solution. For more information on the SelectLink architecture, see Xilinx application note XAPP234. 

When the form below is filled out and submitted, Verilog code for a SelectLink system is generated per the specified parameters. 
The basic SelectLink architecture is specified with three positive integers. They are defined as follows: 

SLintWidth - The width in bits of the internal User Data FIFO Buses in the Transmitter and Receiver. 

SLextWidth - The width in bits of the external Double Data Rate bus (SL). 

NumBlks - Number of SelectRAM+ blocks used in each FIFO (Transmitter & Receiver) 

These three parameters are interdependent, and must satisfy these two rules: 

SLintWidth/NumBlks = 1, 2, 4, 8, or 16 

(2 x SLextWidth)/NumBlks = 1, 2, 4, 8, or 16 

The values of the parameters must fall within the indicated ranges. 

 

SelectLink Verilog
Source Code Generator 

SLintWidth = (2 <= SLintWidth <= 512)
SLextWidth = (1 <= SLextWidth <= 256)
NumBlks = (1 <= NumBlks <= 64)
Note: The depth of each FIFO = (4096 x NumBlks)/SLintWidth
The following parameter may also be configured:
I/O Standard for SelectLink =
After clicking on "Submit", your custom Verilog code will be returned as an HTML display, which can then be saved to your hard drive. To ensure that only the Verilog text is written to the file, do a "Save As" to a file name with a .txt extension. 

After the file is saved, each module may be put in a separate file, with file names of the form module_name.v 

Alternately, the code may be simulated as a single file.

 
Last Update: 3/10/00

 
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