Xilinx CORE Generator IP Updates

XilinxCoreLib Compile Scripts

Compile Scripts for D_IP1

The following PERL compile scripts are provided to help you compile the XilinxCoreLib simulation libraries. To accommodate the dependency of the XilinxCoreLib VHDL library on the Xilinx UNISIM library, the scripts will first compile the Xilinx Unisim VHDL library if needed.
Currently only MTI compile scripts for the XilinxCoreLib VHDL library are available.

Requirements:

The following software must be installed on your system:

Xilinx Foundation iSE or Alliance Series software v3.1i or later
MTI ModelSIM v5.4a or later

Compatibility:

CORE Generator IP Update #1 and #1-c only

Syntax:

xilperl <scriptname>.pl

MTI VHDL (Unix)

compile_xilinxcorelib_mti_vhdl_d_ip1.pl

MTI VHDL (PC)

cxcored1.pl

For information on how to compile the XilinxCoreLib libraries for MTI Verilog, VSS, VCS, or NC-Verilog, please consult the following solution records:

MTI Verilog:

http://suppport.xilinx.com/techdocs/2561.htm

Synopsys VSS:

http://suppport.xilinx.com/techdocs/8015.htm

Synopsys VCS:

http://suppport.xilinx.com/techdocs/6330.htm

Cadence NC-Verilog:

http://suppport.xilinx.com/techdocs/2554.htm


	Trademarks and Patents Legal Information Privacy Policy

Compile Scripts for D_IP1