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CSELT S.p.A
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 Partner Profile
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Overview
CSELT S.p.A is the Telecom Italia Group company for study, research, experimentation,
and qualification in the field of telecommunications and information technology.
CSELT provides a synthesizable Soft IP library - the VIP libraryTM
- consisting of customizable system level cores for designing complex applications
with a new design approach oriented to fast and safe prototyping. VIP libraryTM
is the answer to all Information and Communication Technologies (ICT) product
requirements: system knowledge, technological expertise and time to market. The library
includes cores commonly used in ASICs and FPGAs for Fast Packet Switching (ATM, TCP/IP),
Video and Wireless systems. Cores are available in netlist format and in source code
(VHDL) format. Netlists are released with customized simulation test benches, while
source code is released with hierarchical synthesis scripts and high level programmable
simulation test benches.
The VIP LibraryTM has been used to realize a variety of ICs and
systems for ATM switching and access nodes, Optical Network Units, ATM Virtual Private
Network servers, and switched Digital Video Broadcast equipment.
CSELT's products and services also include:
- Hard macro library: a high performance hard macro IP library including low power
memories, differential low swing pads, PLLs, phase aligners, embedded
- Content Addressable Memories
- Support and user training courses
- IP design methodology courses
AllianceCORE Products
Click here to list all
AllianceCORE products available
from CSELT. Adobe Acrobat versions of the datasheets for these can be viewed or downloaded from the resulting search entries. For information about pricing contact CSELT directly.
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Areas of Technical Expertise
The following table of products demonstrates CSELT's areas of technical expertise.
Xilinx and CSELT are in the process of evaluating these products to determine which
ones are suitable as AllianceCORE products. If you have a need for a specific product
then contact CSELT for information or availability.
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| Product |
Functional Description |
Gates |
| Communications & Networking |
| ATMGEN |
ATM cell generator. UTOPIA level 1 and RACE Pb supported. |
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| ATM_3PRAM |
ATM triple port RAM with FIFO access for ATM streams. |
45,0001 |
| ATMALIGN |
HEC based identification of ATM cell boundaries as specified
in the TIU-T I.432Recommendation. |
30001 |
| FIPO |
First in priority out cell real time sorter based on a fast
partial ordering algorith for ATM traffic shaping and spacing. |
20,0001 |
| FSS |
Frame Synchronous Scrambler cell performs line coding and
decoding of data frames. |
15,0001 |
| IP_GEN |
Internet Protocol cell generator. |
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| MPEG_GEN |
MPEG packet generator. 8-bit MPEG cell transmission. |
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| SDHALIGN |
SDH Frame delineation based on a programmable synchronization
sequence. |
20001 |
| SOFTCAM |
Virtual Content Addressable Memory compresses an input identifier
into a smaller output identifier (like bit strings in ILI, VPI, VCI, and
PTI values in ATM cell header). |
30001 |
| UPARCO/DPARCO |
Upward/downward parallelism conversion of a data stream. |
10001 |
| UTOPIA_L1 |
UTOPIA level 1 interface; PHY side, transmitter and receiver
mode cells. Protocol conversion between UTOPIA and Pb. |
20001 |
| VERCOR |
CRC based error detection and correction on selected fields
of each data block in ATM cell streams. |
10,0001 |
| VQE |
Virtual Queuing Engine to perform push or pop operations
of data (ATM cells) on a logic queue. |
15,0001 |
| Base-level Functions |
| MC68K |
Bus functional model of the MC68000 processor. |
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| MPI |
Generic microprocessor bus protocol. |
20,0001 |
| SDRAM_SGEN |
SDRAM signal generator handles the access protocol to an
external 16 Mbit SDRAM. |
20001 |
| SRAM_INT |
SRAM interface manages access to an external static RAM. |
30,0001 |
| Error Correction |
| RS_DECODER |
Reed Solomon decoder. |
40,0001 |
| RS_ENCODER |
Reed Solomon encoder. |
10001 |
Note:
1. All gate counts are for example implementations and are application
dependent. |
Contact CSELT
Via G. Reiss Romoli, 274
I-10148 Torino
ITALY
Phone: +39 011 228 5259
Fax: +39 011 228 5695
E-mail: viplibrary@cselt.it
URL: www.cselt.it
Use the following form to contact CSELT. To help us better answer your
request for information please list the product(s) you are interested
in and describe the project(s) in the comment field.
When complete, press SUBMIT to send your message. All fields, except
Fax, are required.
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