Background
Xilinx is the first programmable logic company to embrace the concept of cores
for FPGAs with the LogiCORETM
PCI Interface. Today, LogiCORE
products form the most successful core program in the programmable logic industry.
As a result, Xilinx has gained considerable experience developing and selling cores,
and servicing FPGA core customers. Through the AllianceCORETM program,
Xilinx is expanding the availability of quality cores for programmable logic by sharing
what has been learned with leading third-party core developers.
The AllianceCORE program is a cooperative effort between Xilinx and independent
third-party core developers. It is designed to produce a broad selection of industry-standard
solutions dedicated for use in Xilinx programmable logic.
Xilinx takes an active role with its partners in the process of productizing AllianceCORE
products. This is unique to the AllianceCORE program. Because the process is so involved,
we work closely with our partners to select the right cores first which helps raise
the quality and usability of the cores that are offered.
AllianceCORE Product Criteria
A core must meet a minimum set of criteria before it can receive the AllianceCORE
label.
Core Selection
Xilinx looks at cores from a practical point of view. A programmable logic version
of a core must have value over an ASIC or standard product version of the same function.
It must be cost effective and make sense for use in a programmable device in a production
system. If a candidate core does not pass these simple tests, it does not make sense
to invest the effort to convert it to an AllianceCORE product.
Generic, synthesizable cores offer maximum flexibility for users with unique requirements.
This is typically the format for cores provided to the ASIC market. With programmable
logic, however, this flexibility can come at the expense of efficiency and performance.
It can take considerable effort to get a core to synthesize in a way that meets density
and timing requirements in a programmable device. Time spent trying to accomplish
this quickly reduces the time-to-market advantage of using programmable logic and
cores in the first place.
As a result, Xilinx does not promote generic, synthesizable cores
as AllianceCORE products. Instead, they are generally provided as
architecturally optimized fixed gate level netlists. This guarantees
that the implementation is optimized for density while still meeting
performance, preserving the time-to-market value of programmable
logic. Flexibility is provided by allowing you to quickly implement
your unique logic on the same device. Partners may provide cores
customized to meet your specific design needs. Source code versions
of the cores are often available from the partners at additional
cost for those who need ultimate flexibility.
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