Xilinx CORE Generator System

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Overview
CORE Generator Features
CORE Gernator Benefits
CORE Generator Components
CORE Generator Interfaces
Generating a Core
Platform Support
New Cores and Updates

More Information
CORE Solutions Documents

CORE Generator User Guide v3.1i

CORE Generator Cores & IP Updates

Overview

The Xilinx CORE Generator System generates and delivers parameterizable cores optimized for Xilinx FPGAs. Use the Xilinx CORE Generator System to design high-density Xilinx FPGA devices and achieve high performance results while also cutting your design time.

The CORE Generator is included with the Xilinx Foundation, Foundation ISE and Alliance Series software and comes with an extensive library of Xilinx LogiCOREs, including DSP functions, memories, storage elements, math functions and a variety of basic elements. Also included is information on over 90 AllianceCORE functions.

CORE Generator Features

Simple, intuitive operation – Select a core, Enter parameters, and Generate!
Cores are delivered with an optimally floorplanned layout
- Performance is independent of FPGA device size
- Performance stays constant as more cores are added
Detailed functional descriptions and timing diagrams as well as performance and utilization information
provided for each core
Compatible with VHDL, Verilog, and Schematic top-level design flows
Verilog and VHDL behavioral simulation support
Ready access to intellectual property from Xilinx and Xilinx partners
Predictable & repeatable results – core layout is specified up front
Supported on both PC and Workstation platforms

CORE Generator Benefits

Core performance and utilization comparable to the best expert, hand-packed design
Faster time-to-market
- Spend less engineering time and effort by using pre-designed, pre-verified
  cores that can be customized "on-the-fly" to your requirements
- Enjoy fast core generation with proprietary Xilinx software
- Reduce place and route time with pre-placed Cores
Facilitates design reuse
- Build larger, more complex designs faster with cores!
- Reduce design documentation requirements by using larger parameterizable building blocks
- Use the Xilinx IP Capture Tool to integrate your IP into the CORE Generator
- Use the IP Capture Tool to package and share your IP on your company's intranet
Optimal core layout produces lower power dissipation

Xilinx Smart-IP technology produces cores with predictable performance. Core performance is independent of Xilinx FPGA device size and number of cores instantiated, even in large devices. Xilinx Smart-IP technology guarantees that there is no routing interference between multiple cores or between cores and other logic.

No Surprises! – The predictable and repeatable performance of CORE Generator cores allows large FPGA designs to maintain target clock speeds as the design process proceeds. If it is necessary to move to a larger device, the core performance does not change.

The core generation process fabricates the logic for the core, partitions it into configurable logic blocks (CLBs), and then places the CLBs relative to each other. CLB level floorplanning is what makes Xilinx LogiCORE performance so predictable. The relative placement of CLBs making up a core is maintained as the core is integrated into the overall design and placed anywhere in the FPGA.

Xilinx IP Flow

CORE Generator Components

The CORE Generator contains a library of LogiCORE parameterizable cores and AllianceCOREs, along with data sheets for each core. LogiCOREs are designed and supported by Xilinx, while AllianceCOREs are designed and supported by Xilinx AllianceCORE partners.

CORE Generator Interfaces

The CORE Generator CoreLINX interface allows you to bundle and "plug in" cores which your team members may wish to share over the WEB. You can also interface the CORE Generator to system-level tools with the CORE Generator batch mode interface.

Generating a Core

Enter your core parameters, then simply click on the Generate button. The output is an optimized CORE for the targeted FPGA device which includesthe following files.

A tailored Xilinx implementation netlist with complete relative
placement information to guarantee performance
VHDL or Verilog instantiation code
A symbol for schematic capture tools

CORE Generator Platform Support

The CORE Generator supports Windows 98, Windows NT, Windows 2000, and Solaris 2.5 and 2.6 operating systems for PC and Workstation compatibility. No security keys are required.

New Cores and Updates

New plug-in cores that are not already bundled with the CORE Generator can be downloaded from the IP Center web site, or added to the CORE Generator through the CORE Generator IP Capture Tool.


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