Xilinx CPLD WebFITTER
	Xilinx CPLD WebFITTER has broken new ground in evaluating an online silicon solution. By simply selecting the design file and clicking the ‘GO’ button, you are moments away from the industry's best CPLD solution. Whether it's performance, cost, or ease-of-use, WebFITTER has it all.
WebFITTER Features Supports all Xilinx CPLD families XC9500/XL/XV high speed and low cost series  Xilinx CoolRunner XPLA/XPLA2/XPLA3 ultra-low power series. Simple PLD (16V8, 20V8, 22V10, etc...) Accepts the following design formats  VHDL, Verilog, ABEL, EDIF, XNF Competitive conversions for Altera (TDF & TDO) and Vantis (NSR) formats
To use WebFITTER, follow these three simple steps illustrated below.
Step 1: Select the input design file(s) and optionally define synthesis, fitter, simulation and save options. Step 2: You select your targeted device by density, package, speed, voltage, or by automatic device selection. Step 3: Submit your design by clicking . When your design is finished, you receive an e-mail containing a specific URL that links you to the results! Even though the flow through the WebFITTER tool is very simple and intuitive, it has the same capability as is found in the downloadable and desktop versions of the tools. We have also added the ability to target a specific version of the CPLD WebFITTER software for maintaining backward versions of designs. We recommend that you process new designs using the latest version of WebFITTER. WebFITTER provides Links to fitting, timing, and log files Targeted device datasheets Online XC9500 and CoolRunner Series price quotes Simulation and device programming files Online tutorials Complete online Help
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Xilinx WebPACK ISE
	The Xilinx WebPACK ISE contains free downloadable software modules for both CPLDs and FPGAs. Each module provides a simple and intuitive design environment for your target Xilinx PLD family. The WebPACK ISE is a suite of EDA design tools that you can download and use individually or install together for an integrated desktop design environment.
The downloadable software modules include the following:  Design Entry and Synthesis Tools Device Fitter Tools backPACK Tools Device Programmer Tools Design Entry and Synthesis Tools
For designers that do not currently have EDA design entry tools, Xilinx is pleased to offer the Design Entry and Synthesis Tools module; a complete design entry system that includes Xilinx Synthesis Technology (XST) for VHDL and Verilog languages and the latest version of ABEL (v7.3) synthesis engines. WebPACK ISE also introduces schematic capture. Alone, schematic capture is useful for graphical instantiation of HDL modules. In conjunction with the CPLD Capture Libraries backPACK module, you can accomplish primitive level logic design and high level logic block integration.   Design Entry and Synthesis Tools After you download and install this module, the Xilinx Project Navigator will detect if any other WebPACK modules are installed. Once installed, WebPACK ISE modules will provide complete design implementation control within a single project window.   The updated Project Navigator environment included with WebPACK ISE provides a powerful yet simple to use design interface with the following features:  Integrated HDL Editor Expandable Design Processes Third party tools integration Flexible window formatting   Project Navigator's Processes window provides for an intuitive design flow. In addition to synthesis and fitting, the Processes Window allows for automatic launching of the following:  HDL Bencher, a VHDL/Verilog test bench generation tool  Model Technology's ModelSim Xilinx Edition Simulator  ABEL test vector simulation ChipViewer (for XC9500 devices only) FloorPlanner (FPGA devices only) Constraints Editor JTAG Programmer  backPACK Tools
A backPACK is an additional module that provides specific functionality to enhance either your CPLD or FPGA designing process. WebPACK ISE has five backPACK modules:  MXE Starter ChipViewer HDL Bencher CPLD Capture Libraries StateCAD     MXE Starter Xilinx and Model Technology have teamed together to deliver the ModelSim Xilinx Edition (XE) VHDL/Verilog Simulator to Xilinx customers. ModelSim XE is a complete HDL simulation environment that has been optimized for programmable logic design, enabling designers to verify source code and functional and timing models of their design using a common "self-checking" testbench. WebPACK ISE ModelSim XE Simulator includes a complete HDL simulation and debugging environment providing 100% VHDL and Verilog language coverage, a source code viewer/editor, waveform viewer, design structure browser, list window, and a host of other features designed to enhance productivity. This product enables designers who are new to HDL design to experiment with creating HDL designs and test benches. ModelSim XE Simulator has been optimized to use with v3.1i and later design flows which are the basis for WebPACK ISE.   HDL Bencher  HDL Bencher is an automatic test bench generator. Launching HDL Bencher from WebPACK ISE automatically imports the current HDL design file. HDL Bencher analyzes the design I/O and creates a default editable stimulus waveform. Final waveforms can be exported as a VHDL or Verilog testbench file to use in many popular EDA simulators such as ModelSim XE which is also available in WebPACK ISE.   StateCAD  StateCAD automates the state machine design process. Using the FSM wizard, you can specify complex state machines to meet tough product requirements. You can then translate the specified state machine to an HDL format to include in your design flow.   XC9500 Series ChipViewer XC9500 Series ChipViewer (a JavaTM utility) is a pre- and post-fit graphical utility for assigning or viewing pin placement and implemented logic. This tool lists a design's inputs and outputs.    The I/Os are further identified by function block in the post-fit mode. Pre-fit click and drag pin assignment facilitates design constraint editing while post-fit single click pin highlighting assists in design verification. Function block rats nest viewing illustrates design connectivity. Macrocell views provide an equation level illustration of the implemented logic.   CPLD Capture Libraries Xilinx is proud to introduce schematic capture to WebPACK ISE. The basic schematic capture tool is provided in the Design Entry module for HDL designers looking for graphical HDL design capability. The CPLD Capture Libraries are provided as a separate backPACK for those designers who are looking for a more traditional schematic capture tool. Device Fitter Tools
The Device Fitter Tools section consists of three downloadable modules.  All or any combination of these modules can be installed into the WebPACK ISE design environment.    XC9500 Fitter Tools CoolRunner Fitter Tools FPGA Fitter Tools   XC9500 Fitter Tools If you currently own a design entry tool such as a third party synthesis or schematic capture package, the XC9500 Device Fitter Tools module provides all the device fitting and verification tools you need to fit your design into any of the Xilinx XC9500 Series CPLDs.  The XC9500 Device Fitter Tools module is identical to the Alliance Series v3.1i software currently available from Xilinx, except that it is specific to the XC9500 CPLD families. This free downloadable module will accept either EDIF or XNF netlists and provide you with a JEDEC programming file and timing simulation netlist. Constraints Editor Interface LogiBLOX Module Selector Interface   Included Features  Push-button implementation flows Timing driven fitting technology  Fitting and timing reports Internet enabled online Help  LogiBLOX module synthesis Xilinx Constraints Editor  Interactive Timing Analyzer HDL Simprims libraries for third party HDL simulation  Timing Report     CoolRunner Fitter Tools The CoolRunner Fitter module when used in conjunction with the Design Entry and Synthesis module provides a free and complete design environment for the entire CoolRunner series CPLD product line. The CoolRunner Fitter module, under control of the Project Navigator user interface, accepts design netlists prepared using any of the supported third-party Xilinx Alliance EDA vendors. VHDL, Verilog HDL or ABEL language designs can also be created for the CoolRunner device families using the Project Navigator design environment available in the WebPACK ISE Design Entry and Synthesis module.     FPGA Fitter Tools The FPGA Fitter module is useful in configuring WebPACK ISE to support the Virtex V300E and complete line of Spartan-II devices.   WebPACK ISE provides the following functionality for FPGA devices: - Xilinx Synthesis Technology (XST) HDL Synthesis - Timing and I/O constraint editing - Integration with 3rd party tools such as ModelSim, HDL Bencher, and StateCAD. - Multi Pass Place and routing - Design Floorplanning Device Programmer Tools
The Device Programmer Tools section contains two specific software programming modules:  JTAG Programmer (XC9500, FPGAs, and PROMs) XPLA Programmer (XPLA/E, XPLA 2, and XPLA 3)   JTAG Programmer The JTAG Programmer software contains all the software you need to perform IEEE 1149.1 JTAG operations for all Xilinx XC9500 series CPLDs, JTAG-supported Xilinx FPGAs, and Xilinx 1800 Series PROMs. You can run JTAG Programmer as a standalone programming tool or invoke it from within either the WebPACK ISE Project Navigator (CPLD Design Entry and Synthesis Tools module) or from within the Xilinx Design Manager (XC9500 Device Fitter Tools module). Even if you are not a CPLD designer, the Device Programming Tools module allows you to get the latest updates for FPGA device programming!
XPLA Programmer The XPLA Programmer (v4.09) contains the latest ISP device programming software for Xilinx CoolRunner CPLDs, including the new XPLA 3 family.  Included Features Non-CoolRunner CPLD support  ATE automatic vector generation including SVF Automatic programming cable detection for the following download cables: CoolRunner  Xilinx JTAG  Altera Byte-Blaster