FOR IMMEDIATE RELEASE

XILINX NEW ADVANCED DESIGN SOFTWARE ACCELERATES TEN-MILLION GATE DESIGN PRODUCTIVITY FOR VIRTEX FPGAS

Version 3.2i software delivers industry leading speed and unequalled verification efficiency

SAN JOSE, Calif., September 26, 2000—Xilinx Inc. (NASDAQ:XLNX) today announced its newest release of the Alliance SeriesTM and Foundation Series Integrated Synthesis Environment (ISETM) software, version 3.2i. By addressing the challenges of ultra-high density logic design, the 3.2i release improves the Xilinx® design flow by accelerating place and route runtimes and supporting incremental and team design methodologies.

Faster Place and Route, and higher quality of results

This newest software release increases average design performance by an average of 25 percent for its next generation VirtexTM-II architecture. These improvements in automated design performance will ensure that customers choosing Xilinx next-generation products will continue to lead in performance within their respective industries. This advanced design environment is also delivering designer productivity that is two to twelve times faster than any competitors' software.

Incremental design for HDL based design

The version 3.2i software provides guided place and route, integrated together with synthesis tools from Synopsys Inc., Exemplar and Synplicity. This robust incremental design capability enables customers using Xilinx software to change their design in the final stages of the design process, without disturbing the layout and timing of unchanged portions of the design. This capability dramatically reduces the verification time associated with product changes.

Hierarchical floorplanning

The 3.2i floorplanning capabilities provide powerful integration with register transfer level (RTL) level floorplanners, and Xilinx modular design. Hierarchical floorplanning enables synthesis tools to communicate layout and timing directives to the implementation tools, supporting more accurate and aggressive timing estimates during optimization, resulting in higher performance designs. Hierarchical floorplanning is required to achieve optimal performance from incremental design flows when targeting programmable logic devices with HDL as the source. Hierarchical designs also enable the Xilinx modular and team design capabilities, allowing autonomy and high productivity for designers working together on multi-million gate systems. 

Price, platform, and availability

The 3.2i release of Xilinx development systems provides architecture-specific device support for all Xilinx product families, including SpartanTM/XL, Spartan-II, Virtex, Virtex-E, Virtex-EM, and XC4000XTM FPGAs, plus XC9500TM and CoolRunner® CPLDs. The software is compatible for popular PC and workstation platforms and operating systems such as Windows95/98/2000 and Windows NT; Chinese, Korean, and Japanese Windows; Solaris and HP-UX. The new software version pricing starts at $695. The 3.2i software is delivered as part of the Xilinx Alliance Series and Foundation Series design environment.

About Xilinx

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.

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Editorial contact: Product marketing contact:
Ann Duft Craig Willert
Xilinx, Inc. Xilinx, Inc.
(408) 879-4726 (303) 413-3237
publicrelations@xilinx.com craig.willert@xilinx.com