SAN JOSE, Calif., May 18, 1999—Continuing its leadership position in packaging technology, Xilinx, Inc., (NASDAQ:XLNX), today announced new and smaller packages with higher pin counts for the company's mainstream programmable logic devices. This new technology dramatically reduces board space and increases I/O counts for customers. 

Xilinx announced new 144-ball and 280-ball, 0.8-millimeter pitch chip scale packages for the company's SpartanXL FPGA and XC9500 CPLD families. In addition, new 1.0-millimeter FinePitch packages with ball grid arrays ranging from 256 to 680 balls are available for Virtex FPGAs, as is a 144-ball chip scale package for the two smallest Virtex devices. Pitch refers to the center-to-center distance between adjacent solder balls. 

"Today Xilinx provides more I/Os in less space than any competitor in the industry," said Sandeep Vij, vice president of marketing and general manager of the High Volume FPGA Business Unit at Xilinx. "We also are the first programmable logic company to be able to offer 100,000 system gates in a compact chip scale package, a remarkable achievement in itself." 

Chip Scale Packaging Leadership 

Last year, Xilinx was the first programmable logic supplier to offer a 0.8-mm pitch, 48-ball package for the XC9536 CPLD, providing the smallest form factor package in the industry. The proven chip scale packaging (CSP) technology now is available for all members of the XC9500 CPLD and SpartanXL FPGA families. The CSP 144–ball package is also available for the Virtex XCV50 and XCV100 devices, which offer 50,000 and 100,000 system gates, respectively. The chip scale packages are designated as the CS48, CS144 and CS280. 

Chip scale packages are ideal for applications requiring low power and small form factors. The packages are targeted at high-volume, cost-sensitive designs such as digital modems, DVDs and camcorders. CSP packaging for Xilinx CPLDs and FPGAs offers higher I/O density in less board space than 1.0 millimeter pitch offerings available from competing programmable logic devices. Xilinx is the first programmable logic supplier to offer the CSP package for an FPGA that meets the JEDEC Level 3 moisture sensitivity level requirements. This level of reliability enables customers to reduce standard manufacturing cycle times and further minimize overall system cost. 

FinePitch Packaging for Virtex FPGAs 

The new FinePitch ball grid arrays for the Virtex FPGAs feature a 1-millimeter pitch versus the 1.5- and 1.27-millimeter pitches of the conventional BGAs and are gaining wide market acceptance. The Virtex series is the first Xilinx FPGA family to fully support these advanced FinePitch BGA packages. The FinePitch BGAs are available in 256-, 456-, 676-, and 680-ball arrays, require less than half the board space of the previous generation of BGAs, and offer up to 512 user I/Os. The Virtex series provides footprint compatibility within the FinePitch BGA packages of different density devices. The new FinePitch packages are designated the FG256, FG456, FG676, and FG680. FinePitch BGA packages are available for all Virtex devices offering from 100,000 to one million system gates. 

In addition, Xilinx offers a new dimension of flexibility by supplying vertical pin-out compatibility between the FG456 and FG676 packages. This provides system designers the flexibility to layout one printed circuit board for different FinePitch BGA packages, significantly reducing design costs and cycle time.