FOR IMMEDIATE RELEASE
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XILINX ANNOUNCES INDUSTRY'S HIGHEST PERFORMANCE
SAN JOSE, Calif., January 22, 2001— Xilinx, Inc. (NASDAQ:XLNX) today expanded its XtremeDSP initiative by announcing the availability of Turbo Convolutional Encoder and Decoder LogiCORE™ IP products for its Virtex and Virtex-II FPGA families. For the first time, designers can now integrate one or more high-performance turbo code modules into a single FPGA providing the flexibility, performance, and time-to-market advantages needed to meet forward error correction standards of third generation (3G) wireless base stations. The turbo codes are developed in collaboration with Frontier Design and will be discussed at the Xilinx XtremeDSP Technical Simulcast on January 25. The Simulcast will be broadcast live via satellite from the Santa Clara Marriott Hotel and to movie theaters in 45 North American cities. For complete agenda and registration information, visit http://www.xilinx.com/events/seminars/xtremedsp.htm "Not only will the new turbo code FPGA solution significantly reduce development time for 3G wireless infrastructure equipment manufacturers, but it will also allow designers to quickly implement incremental improvements and specification changes of forward error correction schemes," said Babak Hedayati, director of marketing and business development of the IP Solutions Division at Xilinx. "As a result, our customers will have an advantage in the competitive race to implement new wireless standards." The turbo code LogiCORE products provide a single-chip solution with an optional off-chip memory configuration. The Turbo decoder employ the MAX* algorithm and is fully compliant with third generation partnership project (3GPP) specifications (3G TS 25.212 version 3.3.0). By offering bit error rate (BER) performance of 10-6 for 1.5 dB Eb/No and a 2 Mbps throughput for 5 decoding iterations, they are ideal for high bandwidth data-oriented applications. "The compact size of the new LogiCORE products enable designers to construct systems consisting of an array of turbo codes integrated in a single FPGA device while supporting aggregate bandwidth demands of over 20 Mbps throughput," said Dr. Chris Dick, chief DSP architect at Xilinx. "In contrast to the multiple devices required when using traditional ASSPs, these new turbo codes allow communication infrastructure providers to deliver a single-chip solution for 3G base transceiver stations supporting multiple high-data rate subscribers in one cell site." License Price and Availability
The turbo codes where developed in collaboration with Frontier Design whose primary emphasis is a “algorithm-to-silicon” design methodology that greatly improves the creation of Silicon IP blocks starting from customer- proprietary or industry-standard algorithms in the fields of wireless telecom, consumer audio or multimedia applications. About Xilinx
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