Q. What applications are demanding programmable ten million-gate capacity?
The data-intensive systems such as the Internet infrastructure products, voice and video processing systems will require the 10-million-gate capacity to achieve optimal designs.

Q. How does this architecture compare competitor offerings of similar densities?
The Virtex-II architecture is built to support the unique challenges of logic efficient and routing for gate densities to ten million system gates. In particular, the Xilinx patented segmented architecture scales well to higher densities, which allows silicon efficient architectures to be defined to that level. To date, there are no other programmable logic offerings that can match the density.

Q. What software is available to support the Virtex-II architecture now?
Design software is available from through the Xilinx Foundation Series^TM and Alliance Series^TM version 3.1i release and as well as synthesis software from the leading EDA Alliance partners.

Q. What IP will be available for this architecture?
The Xilinx Smart-IP^TM technology allows Virtex IP to be easily ported while preserving relative placement and timing. The Virtex IP that will be available for Virtex-II include key IP for transmissions, communications, networking, DSP, and multimedia. As well, additional IP taking advantage of the Virtex-II architecture are also planned, including a 133 MHz PCI-X core.

Q. What new applications will the Virtex-II architecture be able to address?
The next-generation FPGAs based on the Virtex-II architecture would be ideal for complex networking, wireless base-stations, mass storage, and high-end video server systems. The unique combination of density, performance, memory, and arithmetic capability allows for higher bandwidth capabilities and superior sub-system integration.

Q. Does this new architecture continue the memory-to-logic ratio established with the Virtex-E and EM families?
In today’s high-bandwidth applications, system designers are in constant need of more memory for data buffering to maintain highest throughput in their system. Virtex-II architecture continues the memory-to-logic ratio established in the Virtex series with double the amount of the block RAM and more distributed RAM resources for tomorrow’s data intensive Internet applications. This unprecedented memory-to-logic ratio is unattainable by any programmable architecture available in the market today.

Q. Why does Xilinx find merit in this ratio?
The Virtex-II architecture is targeted for efficient sub-system integration, where overall system bandwidth is directly improved by providing additional buffering on-chip. For telecom, wireless, networking, mass storage, and high-end video and image processing applications, the additional memory is an important part of the high-bandwidth solution to achieve the maximum throughput in the system.

Q. Are other suppliers able to simply add more block memory to match this trend?
The Virtex-II architecture is engineered to meet the need for an abundance of block memories for sub-system function support in network switches, high-end video filtering, and mass storage applications. These applications require both density and performance in order to efficiently use the block memory for overall system performance increases. To date, no other FPGA architectures can provide the level of density nor performance and memory resource, and would have to go through a total redesign in order to achieve the optimal memory-to-logic ratio available with the Virtex-II architecture.

Q. How does Xilinx measure density?
Xilinx measures density in terms of system gates, using the same basic measurement established with the Virtex family. It is a combination of logic, memory, and custom circuit resources that would be utilized in a typical design. The system gate estimate is found in typical designs using a portion of the resources available on the device. This does not count a sum total of all the logic, memory, and custom circuit resources available on each device. Of course, each design uses a different amount of logic and memory, so the density measurement will vary. If a design uses only logic portion of the resources on the devices, the achieved density will be far less than if the design were to use both the logic and a good portion of the memory.

Q. What's different about the read-before-write and no-output-change-write memory modes and why is Xilinx now providing them?
Xilinx has built on the strength of the fourth generation SelectRAM^TM memory hierarchy and add two new write modes for the block RAM to further improve internal memory performance. The two new modes are read-before-write and no-output-change-write modes. 

The read-before-write mode allows users to read from and write to memory in the same clock cycle, thus significantly improve memory performance. For example, for filtering applications in digital signal processing applications where a set of parameters must be continually multiplied and updated, the same memory locations can be read and updated during the same clock cycle, whereby eliminating extra wait states for separating read and write cycles. This feature is also useful for implementing “read-modify-write” operations in shared memory systems, whereby arbitration may be determined by checking on the read contents prior to memory writing. 

The no-output-change-write mode allows user to keep the output port constant while multiple intermediate write operations are performed, which may be used for driving default conditions during multiple write accesses in shared memory systems.

Q. Is this memory capability unique for programmable logic?
Xilinx had pioneered the SelectRAM memory hierarchy to deliver three different high-performance memory resources within a single FPGA device. The SelectRAM hierarchy consists of distributed RAM, block RAM, and seamless interface to external high-performance memories. No other FPGA device provides this level of flexibility. In particular, no other FPGAs provide distributed RAM capability, which allows extremely efficient local pipelining operations and register delayed elements. By utilizing the internal lookup table as 16-b RAM or shift register, which in turn may be cascaded for up to 128-b RAM or arbitrary length shift registers, there is a register increase of over 16 times that in conventional architectures.

Q. How does Virtex-II architecture deliver 0.6 Tera MAC performance?
The Virtex-II architecture is capable of delivering in excess of 600 billion 8-bit multiply-accumulate operations per second (MACs), defined with constant multiplicand arithmetic—the most prevalent multiplication operations in digital signal processing (DSP) operations. Xilinx is able to achieve this performance through innovative technique and is currently in the process of filing the appropriate patent applications. The details are patent-pending.

Q. What is Active Interconnect^TM technology and what are the benefits?
Xilinx Active Interconnect technology, built on the strength of the fourth generation segmented routing technology, provides full buffering at each routing interconnect point. This eliminates the variable routing delay effects of conventional interconnect architectures, where the total routing delay depends on the fan-out. With the conventional interconnect architecture, the routing delay of a particular node may be changed during design iteration, which makes complex designs like the ten million-system gates design impractical. In contrast, Active Interconnect technology allows precise delay calculations that are generally independent of signal fan-out. For complex IP-based designs, Active Interconnect technology allows predictable inter-IP routing delays to facilitate easy integration of multiple complex IP blocks.

Q. What types of packages will be available for the Virtex-II architecture?
The Virtex-II architecture is developed to support both standard wire-bond packages as well as leading-edge flip-chip packages. The flip-chip package accommodates more I/O pins than the traditional wire-bond package by using internal chip area for package connections. Furthermore, the cavity-up nature of flip-chip packages allows superior thermal dissipation through the top of the package. Both the I/O pin-count and thermal advantages are important for complex designs to 10 million system gates and beyond.

Q. Are there plans for any new I/O standards to be supported?
The Virtex-II architecture is designed to support the important Rapid I/O standard used in high-performance networking systems as well as built-in DDR I/O. 

Q. When will the family be sampling and in full production and what will the density range include?
This next generation FPGA family will be first available by the end of 2000 and in full production during the first half of 2001 supporting densities ranging from 50,000 to ten million system gates.

Q. What is the process for the new FPGA products based on this architecture?
The Virtex-II architecture will debut on 1.5V process with eight-layer metal employing copper technology and 0.12-micron L_eff transistors. The architecture is designed for rapid deployment on advanced process technologies of below 100 nm.

Q. What is the anticipated pricing for this family when it first samples?
Pricing will be available at the product announcement.