Xilinx Solution Summary

Xilinx provides significant value in a DSL modem when used to interface various ASSPs together, resolving differences in their interface control signals. The functions typically performed will be in the areas of DMA control, interface controls to the buffer memory, data buffering, or the interface to the host computer. When the host computer interface is a bus standard such as PCI, Xilinx has a 32-bit, 33 MHz PCI solution available for integration into the Xilinx solution.

The in-system programming capability of Xilinx devices enables features to be upgraded while the product is in the field, as well as speeding the time-to-market for the product. The Spartan™XL and the Spartan™-II FPGA or XC9500XL CPLD devices are ideal candidates for this low-cost application, as well as the LogiCORE™ PCI32 core.

DSL Modem Block Diagram (click on a burgundy box for next level of detail or click on a link below)

DSL Market Overview

Most options for increasing modem speed from the standard 56K today to megabit rates involve changing the "wire" - cable, fiber optics, or satellites. But installing fiber optic cable to the home can cost $1-1.5K for ISDN support. ADSL modems use multiple channels on the 700 million existing copper phone lines.

One channel is used for the standard phone line, allowing data and voice to be sent simultaneously. The "A" stands for Asymmetric, referring to the fact that the downstream channel is much faster than the upstream channel (you spend more time getting information from the web than sending it). Maximum rates, depending on distance, are 8 Mbps downstream and 640 kpbs upstream. The telephone company's switching equipment, designed for short-duration telephone calls, is better used by separating data connections onto more efficient equipment. DSL modems are available primarily from the service providers (the telco or ISP). Prices dropped recently to $49/mo from several suppliers for 384 kbps speeds.

Dataquest expects DSL modems to sell 3.7 million in U.S. in 2000, outselling cable and ISDN combined.

DSL Memory Block Diagram

Functions

Interfacing the processor to the memory modules requires at least two critical abilities - electrical compatibility and speed. Electrical compatibility between the processor and chosen memories - FLASH EPROM, SRAM or DRAM is basically resolved by using Xilinx 3.3 volt PLD technologies. Available in both SpartanXL FPGA and XC9500XL CPLDs, the ability to freely connect 5V and 3.3V processors and memories is easily resolved.

For the choice of PLDs to achieve the DRAM interface, either a SpartanXL FPGA or a XC9500XL CPLD could be used to create a mixed 3.3V/5V DRAM interface. The SpartanXL would consume less power than the XC9500XL, however the XC9500XL can typically create a faster DRAM interface if power is not the issue.

For the SRAM and FLASH EPROM interfaces, users frequently want the simplicity of a CPLD for its wide address decode capability and pin retention architecture.

Advantages

Both SpartanXL and XC9500XL devices can be used in a memory interface application such as this. SpartanXL has the advantage of lower operating and standby power while the XC9500XL will offer faster DRAM interface capability and wider decode capability for SRAM, FLASH, or EPROM. Both options are substantially lower priced than competitive alternatives.