The Spartan-II and XC9500 provide the ideal solution for system glue logic between the host CPU and I/O devices within set-top boxes. The SelectI/O feature allows each I/O to conform to many different I/O standards, making Xilinx FPGAs an ideal solution to resolve interfaces between multiple ASSPs. Xilinx FPGAs have been used to provide the CPU memory decoder, interrupt registers, and additional glue logic.

The Spartan-II FPGAs can also provide the perfect programmable system integration vehicle, providing high bandwidth communication interfaces to external devices such as CPUs, memory, and backplane. This eliminates the need for custom logic, expensive clock management schemes, and various translator components including direct interface to backplanes with its GTL I/O capability. Integration of these simple ASSP functions (PLLs, FIFOs, level translators, etc.) can save the set-top designer considerable cost.

By providing flexibility, time-to-market, time-in-market through field upgradability and cost competitiveness Spartan-II FPGAs provide the ultimate set-top box solution.