Netlist/Source file

Specifies the netlist or schematic file that Capture uses to generate the new symbol. Typically, this is the netlist that is associated with the timing information derived from the vendor fitter tool. You can enter the path and name of the file directly, or use the Browse button to select it.

Netlist/source file type

Specifies the format of the netlist or other source file that Capture uses to generate the symbol. If you select a netlist file name using the Browse button, Capture assigns a default vendor file type based on the netlist file extension. Otherwise, you must select a file type from the drop-down list. You can choose from the following netlist or file types:

• Actel Pin File. This file is typically created by the Actel Designer tool.
• Altera Pin File. This file is created by the Altera MAX+PLUS II.
• APD BGA/Die-Text File. This file is created by the Advanced Package Design tool.
• Capture Schematic/Design. A source design or library file from an external file or from the current design. This is automatically set when a schematic folder, which is in a design (.DSN) file or library (.OLB) file, is selected in the project manager at the time the Generate Part dialog box is opened.
• EDIF Netlist. Altera's MAX+PLUS II tool generates an EDIF netlist. You can also use EDIF files from any other source to generate a symbol.
• Lattice JEDEC File. This file is created by Lattice ISP products
• Lattice Pin File. This file is created by the Lattice ispExpert tool.

• Lucent ORCA Pad File. This file is created by the Lucent ORCA tool.
• PSpice Model Library. Used by the PSpice simulator. You can create your own PSpice model libraries using the PSpice Model Editor or use the model libraries that ship with PSpice and install in the Library directory.
• Verilog Netlist. Used for board simulation and for FPGA projects. You can use these netlists to generate a symbol.
• VHDL Netlist. Some vendor tools generate VHDL netlists (with embedded timing information) during place and route. You can use these netlists to generate a symbol.

Netlist/source file type (contd.)

• Xilinx M1 Pad File. This file is created by the Xilinx M1 tool.
• Xilinx Pin File. This file is created by Xilinx place and route tool set.
• XNF Netlist. XNF netlists are the results of the XACTstep place and route tool.

Primitive

Assigns No, Yes, or Default value to the Primitive property. This option is only available for the Capture Schematic/Design source file type. If the value is set to No, you can descend the hierarchy of the placed part instance to see the source schematic.

Copy schematic to library

When this check box is selected, Capture places a copy of the source schematic in the new library created in the Outputs directory of the project manager when a part symbol is generated using a schematic source file. This option is only available for the Capture Schematic/Design source file type. If the part name does not match the source schematic name, the resulting part and schematic will have the same name.

Part name

Specify the name that Capture assigns to the newly generated symbol. If you selected a netlist file name using the Browse button, Capture assigns a default symbol name to this text box that corresponds to the netlist name. Otherwise, you must enter the symbol name directly.

Destination part library

Specifies the name that Capture assigns to the symbol library that will contain the new symbol. If you selected a netlist file name using the Browse button or a schematic file in the project manager, Capture assigns a default symbol library name to this text box that corresponds to the netlist or schematic name and adds a .OLB extension. You can accept the default entry, enter the path and name of the file directly, or use the Browse button to select it.

Create new part

Specifies to create a new part using the specified netlist.

Pick symbols manually

(This check box is available only when you have a PSpice project open)

(This check box is disabled if the PSpice Model Library item is not selected from the Netlist/source file type drop-down list)

Associate a PSpice model to a Capture symbol. When you click the OK button in the Generate Part dialog box, the Model Import Wizard appears allowing you to associate a PSpice model to an existing symbol.

Update pins on existing part in library

Specifies to update the pins on an existing part using the specified netlist, rather than create a new part.

Sort pins

Ascending order

Specify that the pins are sorted in ascending order.

Descending order

Specify that the pins are sorted in descending order.

Additional pins

Specify the number of additional pins on part

Check to specify the number of pins Capture creates for the part. By default, Capture creates only the number of pins required such that each input and output specification in the netlist has a unique pin. However, if you are using a particular device, you may want to specify a number of pins that differs from the number of input and output specifications in the netlist.

Number of pins

Specify the number of pins that Capture generates for the part. This option is only available if you have activated the Specify the number of pins on part check box. Any unused pins on the symbol (pins for which there is no input or output specification in the netlist) are considered I/O pins.

Retain alpha-numeric pin-numbers. Device is pin grid array type package.

Check to retain the alphanumeric pin names for the part (for example, "P20"). This is useful for parts that model Xilinx pin grid array type packages. If the Vendor file type in this dialog box is anything other than Xilinx Pin File or Xilinx Pad File, this option is ignored.

Implementation

Implementation type

Specify the type of implementation. The implementation types available to choose from are the same as those available in the Attach Implementation dialog box.

The most common Implementation type used with the parts created from PLD vendor pin reports is either <none> or Project (which creates a hierarchy of projects for system simulation). Implementation types signify the following:

• <none> Primitive library part.
• EDIF Non-primitive library part. Contents defined by an EDIF netlist generated by a third party EDA tool.
• Project Primitive library part. Associated with the Simulation Resources of an OrCAD Express project for system-level simulation.
• Schematic View Non-primitive library part. Contents defined by a schematic folder/page.
• VHDL Non-primitive library part. Contents defined by a VHDL model.

Implementation name

Specify the name of the attached object.

Implementation file

Specify the path and name of the library or file of the attached object.

FPGA Setup

Open the FPGA Options dialog box. Using this dialog box, you can specify settings for FPGA symbols, FPGA pins, FPGA pin swapping, and pin shape or pin direction.

X and Y

Specify the X and Y coordinates for the jump.

Location Type: Absolute and Relative

Specify if the jump is absolute (to the indicated coordinates), or relative (using the coordinates as an offset to the pointer's current position).

Horizontal

Specify a horizontal grid reference.

Vertical

Specify a vertical grid reference.

Name

Specify a jump to a bookmark. Bookmarks are made using the Bookmark command on the Place menu.

Enter Label

Specifies the label of the state to which you want to return the schematic.

Line Number

Specifies the line number to view in the text editor window.