Glossary

A|B|C|D|E|F|G|H|I|J|L|M|N|O|P|R|S|T|U|V|W|X|Y|Z

A

absolute simulation time
A time measured from the beginning of the simulation.
absolute stimulus
See force.
actual
The value of a parameter passed to a VHDL subprogram.
alias
See net alias, part alias.
ANSI
The acronym for American National Standards Institute.
ARCHITECTURE
A VHDL construct that describes the behavior of a design unit (ENTITY/ARCHITECTURE pair). The ARCHITECTURE can also serve to connect other VHDL design units.
arrow keys
On your computer keyboard, the keys you use to navigate around your screen. Each key is marked with an arrow and is named for the direction in which the arrow points. There is an up arrow, down arrow, left arrow, and right arrow key. Also known as direction keys.
ascend
In a hierarchical design, to move from a child schematic folder to its parent schematic folder. This is done in the schematic page editor using the Ascend Hierarchy command on the View menu. See also descend.
ASCII
The acronym for American Standard Code for Information Interchange. The ASCII character-coding set enables different applications to exchange information.
ASSERT
A VHDL keyword typically used in conjunction with the REPORT and SEVERITY keywords to detect a particular circuit state and announce the condition with an associated severity level.
AutoECO
The acronym for automatic engineering change order. Layout's AutoECO command translates schematic netlist information from Capture to Layout. See also forward annotate.

B

back annotate
To apply modifications to part properties in a schematic folder, such as updating part references and pin numbers, swapping gates, or swapping pins. Properties are back annotated in the project manager, using the Back Annotate command or the Update Properties command on the Tools menu.
bitmap
Bitmaps are graphic images that are made up of pixels, which are the tiny dots on your computer screen. Each pixel in a bitmap is represented by a number between 0 and 255, inclusive, with 0 being the darkest (no luminance) and 255 being the lightest (full luminance). Bitmaps have a .BMP extension, and can be placed on a schematic page using the Picture command from the schematic page editor's Place menu.
BLIF
Berkeley Logic Interchange Format. This format, developed at the University of California, Berkeley, is used to convey Boolean logic between programs. BLIF files are termed PLAs.
bookmark
Just as you can place bookmarks in a book to mark a specific place, you can place bookmarks on a schematic page to indicate a location you would like to return to frequently. To place a bookmark, use the Bookmark command on the Place menu in the schematic page editor. To go to a bookmark when in the schematic page editor, use the Go To command on the View menu. To go to a bookmark when in the project manager, use the Browse command on the Edit menu to display bookmarks in the browse window, and then choose the bookmark.
BRD
An PCB Editor board file. The .BRD contains information about the board, component symbols, pins, nets, keep-ins and keep-outs, plus how the parts are placed and routed. The .BRD file also includes the properties and constraints that apply to parts and areas of the board.
breakpoint
A pause in the simulation triggered by a particular condition. You can set a breakpoint to occur when a certain state exists on a signal, or just before a particular line in a VHDL model is executed during a simulation.
browse window
This window displays the results of queries done using the Browse command from the Edit menu. You can double-click on an object in the browse window to go to that item on its schematic page.
bus
A group of scalar signals (wires) that are never connected to a net. A bus name defines the signals carried by the bus and connects those signals to the corresponding nets. For example, the bus name A[0:3] defines a four-signal bus and connects the four signals A[0], A[1], A[2], and A[3] with nets A0, A1, A2, and A3. See also bus pin, bus entry.
bus entry
A bus entry is used to tie a signal to a bus. The advantage of using bus entries instead of wires is that two bus entries can be connected at the same point on a bus without connecting the signals. If two wires are run directly to a bus at the same location, the signals are connected. See also bus, bus pin.
bus pin
A pin width that can carry multiple signals, as opposed to a scalar that carries only one signal. A bus pin represents all the pins for a bus, and it uses the same naming convention as buses. See also bus, bus entry.

C

CAGE code
Abbreviation for Commercial and Government Entity Code. A number—provided by the federal government to its suppliers—that can be present in the title block of a schematic page.
CELL
An EDIF keyword that defines the interface to a hierarchical block or part. An OrCAD Capture hierarchical block or part will generate a cell in the EDIF netlist. Simulate displays EDIF cells as contexts within the Simulate netlist.
child
In a hierarchical design, a schematic folder whose circuitry is represented by a hierarchical block in the parent schematic folder. To move from parent to child is to descend the hierarchy. This is done in the schematic page editor by selecting the hierarchical block representing the child, and then choosing the Descend Hierarchy command on the View menu. A child schematic folder contains circuitry referenced by its parent schematic folder. The child schematic folder may contain hierarchical ports that connect its signals to signals in the parent schematic folder or to signals on other pages of the child schematic folder. See also ascend.
Clipboard
A temporary storage location used to transfer data between files and between applications. You transfer data to the Clipboard by using the Copy or Cut command on the Edit menu, and you insert data from the Clipboard by using the commands on the Edit menu.
clock
A signal that has a simple repeating waveform pattern. Typically, clocks drive the synchronous devices in your design. Clock stimuli in Simulate can be overwritten by forces.
clock to output delay
The propagation time for a clocked device. That is, this delay is the length of time required for a data signal to propagate to the device output after being clocked.
command line window
Use the command line window to execute a subset of frequently-used Simulate commands.
complex hierarchy
A design in which two or more hierarchical blocks (or parts with attached schematic folders) reference the same schematic folder. See also hierarchical design, simple hierarchy.
context
The level of hierarchy at which logic macros, pins, and signals are found. A context in Simulate corresponds to an EDIF cell or a VHDL ENTITY/ARCHITECTURE pair. A hierarchical block on an OrCAD Capture schematic page appears as a context in Simulate.
convert
An alternate form—such as a DeMorgan equivalent—that can be stored with each part.
cross probing
When intertool communication is enabled in Capture, selecting objects in Capture causes the corresponding objects to be highlighted in PCB Editor. Also, selecting objects in PCB E ditor causes the corresponding objects to be highlighted in Capture. Both applications must be open. See also intertool Communication.
CurrentLocation
A value stored by Capture that determines the starting point for the next macro command. This value is set by the previous macro. You can also set this value by moving the pointer to the desired location, and clicking the left mouse button.

D

DeMorgan equivalent
An electrically-equivalent part based on the DeMorgan rules of equivalence. These rules represent the duality of AND and OR in Boolean expressions: if all AND operations are changed to OR operations, all OR operations are changed to AND operations, and all variables and constants are negated, then the value of the expression remains unchanged. A DeMorgan equivalent can be stored in the convert of a part.
descend
In a hierarchical design, to open and view the child schematic folder represented by a hierarchical block in the parent schematic folder. To descend a hierarchical design, you select a hierarchical block in the schematic page editor, then choose the Descend Hierarchy command from the View menu. See also ascend.
design
The set of schematics and models that collectively define the behavior of your project.
design cache
A local library contained in each project that contains all the parts and symbols used in the design.
design entry
The process of expressing an electronic design. Typically, design entry involves describing a structure using schematic logic macros, behavioral description with a hardware description language (HDL), or some combination of both methods. The design expression is processed to produce a gate-level netlist that can be used for simulation or design implementation.
design implementation
The process of mapping, fitting, or routing your design to or within a specific device. Design implementation can yield timing values that allow you to perform timing analysis and ensure that your design meets your performance requirements.
device-fitter
A software tool to implement a logic design (usually recorded as an Open-PLA or gate-level netlist) into the physical resources of a CPLD.
DIFFERENTIAL_PAIR
Represents a pair of flat nets that will be routed in a way that the signals passing through them are opposite in sign with respect to the same reference. This ensures that any electromagnetic noise in the circuit is cancelled out.
document
A project, schematic page, library, part, or symbol. Each of these is part of a project or a library file. In addition, stimulus files, simulation result files, and simulation models are documents.
DRC
The abbreviation for Design Rules Check, a tool found on the Tools menu in the project manager. This tool checks a project (or a subset of the design) for conformance to a set of configurable design criteria, electrical rules and physical rules for creating netlists.

E

EDA
The acronym for Electronic Design Automation. Software and hardware tools used to ascertain the viability of an electronic design. These tools perform simulation, synthesis, verification, analysis, and testing of a design.
EDIF
The acronym for Electronic Design Interchange Format. A standard published by the EIA (Electronic Industries Association) that defines the semantics and syntax for an interchange format that communicates electronic designs. Simulate uses EDIF 2 0 0 standard netlists as a simulation resource.
ENTITY
A VHDL construct that defines the interface to a VHDL design unit (an ENTITY/ARCHITECTURE pair).
equivalent
See convert, DeMorgan equivalent.
ERC
The abbreviation for Electrical Rules Check, a subset of the Design Rules Check tool found on the Tools menu in the project manager. The ERC matrix is the decision matrix that tells the Design Rules Check tool the conditions to check for when evaluating connections between pins, hierarchical ports, and off-page connectors.
event
Any signal transition that occurs during simulation. An event appears as a transition in the wave window, and generates a new row in the list window. Simulate records the history of all events for any signal that are traced in either window.
external design
Any referenced design that is not included as part of the main design's schematic pages. An external design may be a library (.OLB) part which you can place with the

Part command

from the Place menu. Alternately, an external design may be a complete schematic (.DSN) design which you can include by using the

Hierarchical Block command

from the Place menu. Whenever you use external designs you set up a hierarchical structure. If you copy an external designs without taking into consideration the occurrence properties inherent in a hierarchical structure, you might get instance property but not occurrence values.
Note: Except for occurrence properties, the schematics of externally-referenced libraries and designs should not be edited. You should view them as read-only designs. Trying to edit, then save, these designs from within your schematic can introduce errors such as duplicate reference designators and other problems.
When saving schematics with externally-referenced libraries or designs, occurrence properties are saved but altered instance values are not. If you want to change externally-referenced libraries or designs you should first close the referencing design. Then, open the referenced library or design, make the necessary changes, and save and close the referenced library or design. At this point, you can reopen the original design and reference the modified design.

F

flat design
A schematic folder structure without hierarchy (no hierarchical blocks or ports; no parts with attached schematic folders). A flat design can include schematic pages in which output lines of one schematic page connect laterally to input lines of another schematic page through objects called off-page connectors. You place off-page connectors using the Off-Page Connector command on the Place menu in the schematic page editor. Flat designs are practical for small designs with few schematic pages. See also hierarchical design, complex hierarchy, simple hierarchy.
flat net
A type of net represented by a flattened (non hierarchical) netlist for a PCB, such as a layout netlist.
force
A scheduled state change that occurs at a specific simulation time. A force will override any other signals driving the node. That is, a force is equivalent to placing a probe on the node. When you place a force, it remains in effect until you replace it with another force, or until you remove the force from the stimulus file.
forward annotate
The process of sending netlist data in the form of a .BRD file from Capture to PCB Editor.
functional simulation
Simulation that verifies design logic and functionality without regard to timing (for example propagation or critical path).
fuse plot
An ASCII representation of a fuse map. You can use this file to visually review the fuse map that Express creates for your simple PLD. Fuse plots appear as shown in the following example:

FUSE MAP FOR P12H6

 

 

 

 

G

globals
Power symbols and ground symbols. Could also be other objects that function the same as power or ground.
graphic object
An object drawn or placed on a schematic page or part -- such as an arc, line, rectangle, ellipse, polygon, image, or text -- that has no electrical connectivity.
grid references
The border around a schematic page that provides a visual reference to the grid. Grid references can be used as a destination for the Go To command on the View menu. Grid references can be set to visible or hidden in both the Design Template and Schematic Page Properties commands on the Options menu.

H

heterogeneneous part
A package with multiple parts that are graphically different or contain different numbers of pins (for example, a relay). See also homogeneous part.
hierarchical block
A symbol that refers to a child schematic folder in a project. The connection points on a hierarchical block are called hierarchical pins and hierarchical ports. You place a hierarchical block using the Hierarchical Block command on the Place menu.
hierarchical design
A project structure in which schematic folders are interconnected vertically with hierarchical blocks. At least one schematic folder, the root schematic folder, contains symbols representing other schematic folders. See also complex hierarchy, simple hierarchy, flat design.
hierarchical pin
A symbol, placed within a hierarchical blocks, that represents a signal connected to a like-named hierarchical port on another schematic page. You place a hierarchical pin using the Hierarchical Pin command on the Place menu.
hierarchical port
A symbol that specifies that a signal on one schematic page connects to a hierarchical pin on another schematic page. A hierarchical port includes a name and a type (either scalar or bus). You place a hierarchical port using the Hierarchical Port command on the Place menu. See also hierarchical block.
homogeneous part
A package with multiple parts that are graphically identical. See also heterogeneneous part.
HPGL
Acronym for Hewlett-Packard Graphics Language, which is a plotter protocol.

I

IEEE
Acronym for Institute of Electrical and Electronics Engineers.
IEEE Std VDHL 1076
VHDL standard determined by the Institute of Electrical and Electronics Engineers.
implementation path
The path for an attached object, such as a referenced design folder or a library part.
inherent property
One of the set of properties required for a given object. Unlike user defined property, inherent properties cannot be removed.
instance
A part or a symbol that you have placed on a schematic page.
instance property
A user property applied to the placed instance of a part or symbol in the design. This includes PCB Footprint, Value, and Name properties of each placed part or symbol in a design. This is the same as the user properties displayed and editable from the Capture v7.2 Physical view.
An instance property will "shine through" to all occurrences of that instance unless it is overridden by occurrence properties that you have edited. A change using any of the tools, like Annotate, also may update the instance property.
intertool Communication
Abbreviated ITC. A capability that allows OrCAD EDA tools to share information for display and transfer.
ITC
Intertool Communication. A capability available with OrCAD for Windows tools that allows these tools to share information for display and transfer.

J

Junction
A junction, shown as a small dot, is placed at the connection point where two perpendicular wires or buses cross, to give visual confirmation that the items are electrically connected. If you draw a wire across another at a 90-degree angle, the wires are not electrically connected unless you create a junction by clicking the left mouse button on the existing wire as you draw the new wire across it.

L

library
A collection of often-used parts, graphics, schematic pages, and symbols.
library definition
A package property or user property associated with the part in the library.
A library definition will "shine through" to the instance and occurrences of that part property. Shine through is indicated by hash marks in the cell. You can assign a value to it creating an instance property. The instance property then will override the shine-through definition.
location
An X, Y coordinate on the schematic page or part. You can move to a location using the Go To command on the View menu.

M

macrofunction
A high-level building block made of two or more primitives. Muxes, counters, and adders are examples of macrofunctions.
MDD
PCB Editor Module Definition File (.MDD). This is the file type created in PCB Editor once you've designated the extents of a reuse module and specified a module origin. Each physical module is assigned a REUSE_MODULE property and contains placed and routed components.
mirror
To flip along the X (horizontal) or Y (vertical) axis, or both.

N

net

1. All of the wires, buses, parts, and symbols that are logically connected via net names, net aliases, off-page connectors, and hierarchical ports.
2. A general electronic term for a circuit node that ties a collection of component pins together. The EDIF 2 0 0 netlist format contains a netlist region that declares the net name and all component instances that are tied to it. You can trace EDIF nets in Simulate.
   net alias
   A name used to specify signal connections between unconnected wires or buses. For example, if you have wires in two remote locations in a schematic page, you can assign each wire an alias such as "ABC" to connect the signals without physically drawing a wire between them.
   netlist
   A file, usually ASCII, that lists the interconnections of a schematic folder by the names of the connected signals, parts, and pins.
   nonprimitive
   A part with an underlying hierarchy, such as an attached schematic folder.

O

occurrence
A user property applied to multiple occurrences of placed instances of parts or symbols in a design. This is the same as the user properties displayed and editable from the Capture v7.2 Physical view.
The spreadsheet will expand to display occurrence properties if values are different from the instance shine through value; otherwise, the rows are hidden from view. To quickly hide or display all the occurrence properties, press and hold the CTRL key while clicking on one of the plus (+) symbols in the property editor.
A change using any of the tools, like Annotate, also may update the instance property.
off-page connector
An object that conducts signals between schematic pages within a schematic folder. See also flat design, hierarchical port.

P

package
A physical part that contains more than one logical part. For example, a 2N3905 transistor, a fuse, and a 74LS00 are packages. Each part in a package has a unique part reference comprised of a prefix common to all the parts in the package, and a letter unique to each part. For example, a 74LS00 whose part reference prefix is U15 would have four parts whose part references are U15A, U15B, U15C, and U15D. See also homogeneous part, heterogeneneous part.
pan
To change the portion of the schematic page or part being viewed by dragging objects from one location to another. As you drag the object, the schematic page or part pans across the active window.
parent
A schematic folder that contains a hierarchical block that refers to another schematic folder (called a child schematic folder).
part
A part is a basic building block of a design. A part may represent one or more physical components, or it may represent a function, a simulation model, or a text description for use by an external application. A part's behavior is described by a SPICE model, an attached schematic folder, HDL statements, or other means. Parts usually correspond to physical objects—gates, connectors, and so on—that come in packages of one or more parts. Packages with more than one part are sometimes referred to as "multiple-part packages". See also package.
part alias
A duplicate copy of a part using a different name in a library. A part alias uses the same graphics, attached schematic folders, and properties as the original, with the exception of the part value.
part editor
The editor used to create and edit parts and symbols.
part instance
An instance property of a part.
part primitive
See primitive.
part property
A part property is a characteristic of a part that can be edited. A property consists
of a name and a value. Examples of property names are part value and color. Their
respective property values can be something such as capacitor and red.
part reference
When you place parts on a schematic page, all parts of the same type are assigned the same part reference. For example, C? is assigned to all capacitors. Regardless of the ultimate purpose of your design, each part needs a unique part reference. You can assign part references by editing individual parts in the part editor, or, for PCB designs, by creating a swap file to use with the Back Annotate tool.
If you want to incrementally update a design in which some of the schematic pages have already been updated, you can use the Annotate command to remove part references from those schematic pages.
pattern
A set of events that occur on a signal, relative to a specific simulation time. This pattern may or may not be repeating. Patterns may be overwritten by forces. Conflicts between patterns, or between a pattern and signal propagation are resolved using signal contention resolution.
PCB
Abbreviation for printed circuit board.
pending event
A simulation event that will occur in the future. As signals change state during simulation, a VHDL simulator must evaluate the input stimuli and all design units of the circuit, then anticipate or schedule all events that must be reported before the simulation time can advance. Simulate allows you to view pending events with the Pending Events command.
pin
A pin acts as a point of connectivity for the part it is attached to. In addition to input and output pins, there are also 3-state, bidirectional, open collector, open emitter, passive, and power pins. If a pin connects to a wire, it is a scalar pin; if it connects to a bus, it is a bus pin. See also hierarchical pin.
pin delay
The propagation delay for a pin to pin transition. That is, pin delay is the length of time required for the effects of a signal at an input pin to be reflected at the corresponding output pin(s).
pin swap
The exchange of identical pins in order to decrease route lengths.
pin to pin spacing
The physical spacing between pins on a device.
PLA
A file that uses the BLIF to express Boolean logic. Typically, PLA files are used as entry mechanisms for simulation models into Simulate.
place and route

1. A software tool to implement a logic design (usually recorded as a gate-level netlist) into the physical resources of an FPGA.
2. The process of determining a design layout in order to estimate routing delays and predict design performance.
   PLD
   Abbreviation for programmable logic device.
   Preferred mode warning
   Capture automatically sets the preferred mode based on the project type. FPGA and PSpice projects default to use instances, while PCB and Schematic projects default
   to occurrences.
   polygon
   A graphic object made up of polylines (multiple contiguous segments) whose beginning and end are attached to form a closed shape that can be filled.
   polyline
   A line with multiple contiguous segments. You place a polyline using the Polyline command on the Place menu.
   port
   A VHDL term for an interface element of an ENTITY. A port serves as a communication channel between VHDL design units. A part pin on an OrCAD Capture schematic page generates a VHDL port. See hierarchical port.
   primitive
   A part or hierarchical block with no underlying hierarchy.
   programmable logic device
   A type of integrated circuit whose behavior can be determined by programming it. Abbreviated PLD.
   project
   An OrCAD project file (.OPJ) includes references to all of the resources you use throughout the design process. These resources including elements that define design structure (VHDL source files, schematic folders, etc.), as well as part libraries, test benches, stimulus files, simulation models, vendor files, and standard delay files. You can view these resources in the project manager.
   project manager
   The project manager is a tool that allows you to collect and organize all the resources you need for your project throughout the design flow. These resources include schematic pages, part libraries, and netlists, and may also include VHDL models, simulation models, timing files, stimulus files, and other related information.
   PROPAGATION_DELAY
   Defines the minimum and maximum propagation delay constraint between any pair of pins in a net. By assigning this property to nets, you can make the router restrict the length of interconnect to meet timing margin. This property often is best applied to a common clock sourced designed bus.
   property
   A characteristic of an object that can be edited. A property consists of a name and a value. Examples of property names are part value and color. Their respective property values can be something such as capacitor and red.

R

radix
The number base in which a signal value is displayed: binary, octal, signed or unsigned decimal, or hexadecimal.
RAM
Abbreviation for Random Access Memory. This is the memory that can be used by applications to perform necessary tasks while the computer is on. When you turn the computer off, all information in RAM is lost.
random access memory
The memory that can be used by applications to perform necessary tasks while the computer is on. When you turn the computer off, all information in random access memory is lost. Abbreviated RAM.
RATSNEST_SCHEDULE
Specifies the type of ratsnest calculation that Constraint Manager performs on the net. By using the RATSNEST_SCHEDULE property, you can meet a balance between time margin and noise margin. This property is useful for defining the placement of receiver or driver in multi-drop buses and asynchronous signals.
recursive design
A hierarchical design in which a schematic folder in the hierarchy is attached to a part instance or hierarchical block placed "higher" in the hierarchy. The simplest case of recursion is some schematic folder X containing a part instance or hierarchical block to which schematic folder X is attached.
reference designator
The designator, or identification code, for a component. A reference designator uniquely identifies a part in a design. For uniquely identifying parts, you can use the Annotate command on the Tools menu. For PCB designs, the Annotate tool assigns individual parts to a package and assigns unique pin numbers to each part in a multiple-part package. References are assigned in order from top to bottom and left to right; parts located at the top of the page have the lowest numerical designation. If two parts share a vertical coordinate, the part further to the left has the lower numerical designation.
The format for reference designators should never be changed as <Alphabet(s)><Numeric><Alphabet(s)> or <Alphabet(s)>-<Alphabet(s).
RELATIVE_PROPAGATION_DELAY
An electrical constraint attached to pin-pairs on a net. It specifies a group of pin-pairs that are required to have interconnect propagation delays matching a specified delta (offset) and tolerance with respect to the target pin pair. You can apply the RELATIVE_PROPAGATION_DELAY property to a source synchronous bus design, such as DDR interfaces.
root schematic folder
The schematic folder at the top of a flat design or hierarchical design. The root schematic folder contains a backslash ( \ ) in its icon in the project manager. A project has only one root schematic folder.

S

scalar
A pin width that carries only one signal, as opposed to a bus pin that can carry multiple signals.
schematic folder
A collection of the schematic pages at the same level of hierarchy in a design is contained within a schematic folder, which is shown in the project manager. See also flat design, hierarchical design, schematic page, root schematic folder.
schematic page
A page within a schematic folder on which a design is drawn. Schematic pages display in a window called the schematic page editor, in which you can place parts and draw wires.
schematic page editor
The editor used to create and edit schematic page.
SDF
Standard Delay File. This is a file containing delay values that relate design performance after place-and-route. You can add this file to your simulation project in order to perform timing analysis.
session frame

1. The Capture application window in which the various components of Capture—such as the session log, project manager, schematic page editor, and part editor—run.
2. The Simulate application window in which the various components of Simulate—such as the session log, wave windows, list windows, watch window, and project window—run.
   session log
   A window that displays text messages generated by Capture, such as errors and informational messages. The session log starts empty with each new Capture session, but you can save its contents to a text file.
   setup time
   The length of time for which data must be stable at a pin before being clocked into the device.
   signal
3. An electrical impulse of a predetermined voltage, current, polarity, and pulse width.
4. The logical state that exists on a circuit node.
5. A VHDL term for a local circuit node that is not visible outside a VHDL design unit. A bus or wire on an OrCAD Capture schematic page that is not connected to a hierarchical port produces a signal.
   signal contention
   A condition that occurs when a circuit node is driven by multiple conflicting sources at the same time. In most circuit nodes, output-type ports fan out to drive multiple input-type ports. However, some networks are constructed such that it is possible for multiple drivers to drive a single node. Simulate uses MVL-9 signal contention resolution to resolve these conflicts.
   signal context
   The level of hierarchy at which a signal or port exists.
   simple hierarchy
   A project in which there is a one-to-one correspondence between hierarchical block (or parts with attached schematic folders) and the schematic pages they reference. Each hierarchical block (or part with attached schematic folder) represents a unique schematic page. See also hierarchical design, complex hierarchy.
   simulation model
   VHDL descriptions of the behavior of primitive components in your design. Typically, the simulation models for your design will exist in a single VHDL file, but they may also exist within the netlist file or in several different model files. Simulation models are necessary elements in an Simulate project.
   simulation project
   A simulation project is a collection of the resources you need to simulate your design. Generally, a simulation project requires the following elements: a netlist, a set of simulation models, and a set of stimuli. In addition, your simulation project may include timing annotation files after it has been through the design implementation process.
   simulation resolution
   The amount of time that represents one "step" in a simulation run. Simulate has two resolution settings: nanoseconds (the default) and picoseconds.
   source library
   The path and filename of the part definition. A filename with an .OLB extension means that the part was placed as is from a library. A filename with a .DSN extension means that the part no longer match the original library definition and its current definition only resides in the design file where it was edited.
   spreadsheet editor
   A window used to edit the properties of multiple objects at once.
   split part
   A part that consists of a package in which pins are split across multiple sections.
   static timing analysis
   A process that inspects the layout of a PLD or FPGA design to estimate the timing characteristics of the manufactured device. Typically, static timing analysis generates a delay annotation file for a digital simulator.
   stimuli
   Signal states that are applied to nodes in an electronic design in order to view the effects of those states on circuit behavior. There are three types of stimuli in Simulate: forces, patterns, and clocks.
   subprogram
   A term used to refer, collectively, to VHDL functions and procedures.
   symbol
   The graphical object that represents a part on a schematic page.

T

tabbed dialog box
A dialog box that has different views you can display by clicking on tabs at the top of the dialog box.
test bench
A VHDL module that defines the interface to one or more designs under test, applies input vectors, and (optionally) generates reports about the output behavior of the design(s) under test. A test bench ENTITY does not provide communication ports; therefore, test benches are usually used exclusively by VHDL simulators.
timing analysis
Simulation that identifies timing problems in the design. Timing analysis is performed after design implementation.
timing annotation file
A file containing delay values associated with the implementation of a design. In general, timing annotation files are produced from place and route tools.
timing violation
A simulation condition indicating that the timing constraints for a device have been violated. Simulate detects timing violations via the error trapping of VITAL VHDL models.
tri state enable delay
The length of time required for a tri-state device to transition from a Z state to a 0 or 1 once an enable has been received.
True Type
A font (typeface) that appears in a printout exactly the way it appears on the screen. TrueType fonts are scalable to any font size, and several of these type of fonts are installed automatically when you install Windows.
twos complement
An alternate method for representing a binary value. Two's complement allows positive and negative values to be represented in the same format and thus enhances arithmetic operations. The most significant bit of a two's complement value is the sign bit: a "0" indicates a positive value; a "1" indicates a negative value. The two's complement of a value is derived by inverting each bit in that value, then adding 1 to it. Thus, the binary value 0111 (representing +7) becomes 1000+1, or 1001 (representing -7).

U

user defined property
A property[ you add to an object. Unlike |Glossary#1026858]inherent properties, user-defined properties can be removed.

V

vertex
The point at which the sides of an angle meet. You create this by drawing a wire or line in one direction, then changing direction to create an L-shaped or V-shaped wire or line.
VITAL
VHDL Initiative Toward ASIC Libraries. An informal consortium formed to accelerate the development of ASIC macrocell simulation libraries modeled with VHDL.

W

waveform pattern
A set of events that occur on a signal, relative to a specific simulation time. A waveform pattern may or may not be repeating.
wildcard
A symbol, usually used in searches, that represents a missing or unknown character or sequence of characters. Valid wildcard characters are an asterisk (*) to match multiple characters and a question mark (?) to match individual characters.

X

X axis
The horizontal or left-to-right direction in a two-dimensional system of coordinates. The X axis is perpendicular to the Y axis.
XNF
Xilinx Netlist Format. This is a netlist format generated by Xilinx design implementation tools. You must convert XNF files to VHDL format before you can use them with Simulate.

Y

Y axis
The vertical or bottom-to-top direction in a two-dimensional system of coordinates. The Y axis is perpendicular to the X axis.

Z

zoom
To change the view of a window, making objects appear larger or smaller. When you zoom out, objects are smaller, and you see more of the schematic page, part, or waveform pattern. When you zoom in, objects are larger, but you only see a small portion of the schematic page, part, or waveform.
zoom factor
The amount by which the zoom scale is multiplied or divided when you choose Zoom In or Zoom Out on the View menu. The Zoom factor is normally 2, but you can change it using the Preferences command on the Options menu. For example, a zoom scale of two makes the image on the screen twice as large when you zoom in and half as large when you zoom out. You can also zoom in or out of a print preview.
zoom scale
The relative size of the image on the screen, as a percentage of the normal size. For example, a zoom scale of 250% means the image on the screen is two and one-half times as large as normal.