Here's my point of view on a possible charter, scope,
and set of deliverables for DC-WG.
Mark
---Charter ------- The Design Constraints Working Group is chartered with developing a standard for describing a variety of constraints, assertions, and environment conditions. These collectively represent the designer's intent for a number of aspects of the design besides the logical functionality, which is described by other standards.
Scope ----- The standard should be language-independent, initially supporting chip and module level designs done in a mixture of Verilog, VHDL languages. Later work should add support for mixed-signal designs and corresponding design languages. Board level designs are covered by other standards such as RAIL and are not within the scope of DC-WG. However, there is significant overlap, and DC-WG should strive for semantic consistency in the areas of overlap.
The standard should address required performance characteristics, implementation details, and descriptions of (as well as restrictions on) the environment in which the design is to be used.
The standard should cover a number of different domains, including timing, area, power, signal integrity, logic architecture, clocking, physical design, test, manufacturability, and reliability/lifetime. The initial focus should be timing.
Some physical design constraints are also addressed by the Physical Design Exchange Format (PDEF) standard, and DC-WG should define the relationship between the two standards.
Deliverables ------------ A constraint dictionary, which is a concise catalog of the different types of constraints, assertions, and environment conditions. Included in the constraint dictionary will be a name for each constraint, a list of the possible parameters, and a brief description of the semantics.
A specification document for a constraint command language, suitable for user entry. Included in the specification document will be a complete description of the syntax and semantics for each constraint and its parameters.
A golden parser and syntax checking program for the constraint command language. The syntax checker should read a constraint command file and report all syntax errors but will not check for semantic errors. The program will be placed in the public domain.
-- Mark Hahn phone: (408) 428-5399 Architect, Deep Submicron Business Unit fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com