Attendees:
Mark Hahn, Cadence (Chair)
Tom Dewey, Mentor
Steve Grouts, Sematech
Enrico Malavasi, Cadence
Cynthia Parrish, Exemplar
Greg Schulte, Ambit
Jim Swift, IBM
Next Meeting:
The next meeting will be a teleconference on Tuesday, 6/23/98,
from 9-11 PDT.
Action Items:
Who When What
---------- ------ --------
1. Mark 6/9 Fix broken links on the web site
2. Mark 6/22 Investigate RAIL and get documentation on it
3. Mark 6/22 First draft of taxonomy for clocking
4. Greg 6/22 First draft of taxonomy for exceptions
5. Steve 6/22 First draft of taxonomy for parasitics
boundary conditions
6. Jin 6/22 First draft of taxonomy for timing boundary
conditions
7. Mark 6/22 Write up an extended description of how modes work
8. Greg 6/22 Write up an extended description of how tags work
9. Jim 6/22 Write up an extended description of how operating
conditions work
10. Mark 7/7 Arrange for a face to face meeting at ICCAD
Details:
1. Constraint taxonomy discussion
We reviewed the skeleton document. The format should be
changed slightly, to use a smaller font and to include a
page break between constraints.
2. Tags
We talked about tags associated with arrival and required
times, a feature of the Ambit constraint language. Tags
apply when modeling the constraints at the boundary of a
hierarchical block or a chip. In most tools, there can be
different arrival (required) times at an input (output) pin,
one for each of the clock signals associated with registers in
other blocks which are in the cone of logic ending (starting)
at the input (output) pin.
With tags, there may be several different arrival (required)
times with respect to the same clock, and a unique tag is used
to distinguish between them. The value of this is in modeling
false or multi-cycle exceptions which span the boundary of the
block. Suppose there are two partial paths, A and B, starting
outside the block and ending at an input pin, and two partial
paths, C and D, starting at the input pin and ending inside the
block. If the full path consisting of A and C is false, but the
other three paths (A+D, B+C, B+D) are not, the normal approaches
to describing arrival times and setup/hold arcs break down, because
they describe the worst case across all partial paths.
Tags are used to distinguish between different classes of partial
paths. In the example, A and B would be modeled as two separate
arrival times with different tags. Then a false path constraint
would be specified for the combination of A's tag and path C.
3. Modes
We talked about modes and case-dependent constraints.
The basic idea is that complex blocks in a design will often
have several different modes of operation. The characteristics
of the block and the timing constraints on paths connecting
to the block will vary depending on the mode. For example,
IBM latches have several modes, corresponding to normal
operation and test operation. Modes can be viewed as an
extension to state-dependent modeling, where each mode
corresponds to a named state.
Case-dependent constraints are used in conjunction with modes
to enumerate valid combinations of modes across different blocks.
The simplest use is to specify constant values for signals. GCF
provides a general mechanism for specifying the default case as
well as a independent sets of constraints for other cases.
4. Operating conditions
We talked about a variety of issues related to operating conditions.
The basic idea is that analysis and optimization need to take process,
voltage, and temperature variations into account. Traditionally
this has been done as a best case, worst case analysis which models
variations between different samples of a chip.
More recently, people have started doing analysis of variations within
the same chip (intra-die). This relates to
- IR drop analysis
- multiple voltages on the same chip
- blocks whose voltage is state-dependent
- best case, worst case parasitic estimation/extraction
- best case, worst case crosstalk
For clock trees, some people want analysis and optimization
of insertion delay and skew to simultaneously consider both
intra-die variations and different sample variations.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Architect, Deep Submicron Business Unit fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com