DC-WG: 6/9 meeting minutes

Steve Grout (grouts@bootskut.eng.sematech.org)
Mon, 22 Jun 1998 16:38:51 -0500 (CDT)

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Mark -

> 5. Steve 6/22 First draft of taxonomy for parasitics
> boundary conditions
> ...

Mark - please give me a sanity check on this. I am interpreting the
above, per our brief conversation at SLDL, that my scope initially
includes all definitions about parasitics with respect to timing,
e.g.,

...
- pin capacitance to substrate
- pin drive
- pin loading
- netsegment lumped capacitance to substrate
- netsegment lumped capacitance to some other netsegment
- netsegment per unit capacitance to substrate
- netsegment lumped serial resistance
- netsegment per-unit serial resistance
- netsegment lumped self-inductance
- netsegment per-unit self-inductance
- netsegment lumped mutual-inductance to some other netsegment
- netsegment per-unit self-inductance resistance to some other netsegment
- power supply drive effective impedance
- ground/substrate effective impedance
- substrate thermal impedance
- substrate per-unit-area thermal impedance
...

with the definitions applicable to today's ASIC practices as well
as the coming VDSM (250nm and below down to 100nm) RLCM distributed
parasitics etc.

I am also in agreement with the below discussion. We here are working
to get supplier support for distributed RLCM parasitics with best/worst/
nominal values including process sensitivities.

> We talked about a variety of issues related to operating conditions.
> The basic idea is that analysis and optimization need to take process,
> voltage, and temperature variations into account. Traditionally
> this has been done as a best case, worst case analysis which models
> variations between different samples of a chip.
>
> More recently, people have started doing analysis of variations within
> the same chip (intra-die). This relates to
> - IR drop analysis
> - multiple voltages on the same chip
> - blocks whose voltage is state-dependent
> - best case, worst case parasitic estimation/extraction
> - best case, worst case crosstalk
>
> For clock trees, some people want analysis and optimization
> of insertion delay and skew to simultaneously consider both
> intra-die variations and different sample variations.
>
> Thanks,
> Mark

I have several sets of materials from which to take definitions from so
I can avoid as long as possible inventing adhoc definitions.

Talk to you tomorrow on the telecon.

Regards,
--Steve

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