DC-WG: 2d try - first cut at hierarchical parasitic boundary conditions

Steve.Grout@SEMATECH.Org
Tue, 21 Jul 1998 17:16:28 -0500

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--Boundary_(ID_88f7AOFiuQx3RkzNT5k94g)
Content-type: text/plain

Here is my draft of the hierarchical parasitics at the boundaries.

There are really 3 parts to my draft 'Section 3'
- general discussion about lumped evolving to fine grain coupled
parasitics
- the current list of terms which include now the applicable ones from
the Ambit offering.
- a very minimal start at the actual tables.

I will be trying flesh this out to the same level as the others in the
next couple of days.

Regards,
--Steve Grout
SEMATECH
--------------------------------------------

--Boundary_(ID_88f7AOFiuQx3RkzNT5k94g)
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************************************************************************=
****
\par DCWG reviewers: This draft section is best =
described as being in 3 parts.
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\fs20\cgrid {A general discussion of parasitics from the point of view =
of external or interface ports of a=20
block definition and instance (potentially occurrence) ports of a block =
instance (boundary conditions). I hope the terminology I use wont get =
in the way of your review, however, once one goes fully hierarchical, =
then we have to become more specific than,
for instance, \lquote external\rquote . The discussion also covers =
the several levels of parasitics that are coming, e.g., distributed RC, =
RCL, and RCLM, all which need to include coupling.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li1080\sb120\nowidctlpar\widctlpar\jclisttab\tx1080{\*\pn=
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
My current list of list of hierarchical parasitics at the boundaries =
of blocks in a design hierarchy. I am in the process of redoing the =
appropriate ones to reflect those offer within the Ambit synthesis =
constraints document.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li1080\sb120\nowidctlpar\widctlpar\jclisttab\tx1080{\*\pn=
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
A first cut at fleshing the list of hierarchical parasitics at the =
boundaries of blocks in a design hierarchy
\par }\pard\plain \qj\sb120\nowidctlpar\widctlpar{\*\pn =
\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\adjustright \fs20\cgrid { =
************************************************************************=
** >>>
\par This section defines the Parasitic Hierarchical Boundary =
Conditions needed to define and constrain the timing of signals being =
carried by a net and applicable operating e
nvironment conditions. These may be defined from within the design =
descriptions and/or from tools and/or by the designer/user.=20
\par The scope of this section includes the following coverage and =
points of view:=20
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright=20
\fs20\cgrid {This section defines the boundary conditions tha
t surround any particular net or fragment of a set within a block =
within a design hierarchy. The boundary conditions therefore define =
the specific environment for defining (prescribing) and/or constraining =
the timing of signals being carried by a net.

\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {Ele
ctrical, magnetic, optical, thermal, (and possibly other forms of =
energy), material, and mechanical properties that drive (source, =
transmit), load (sink, receive, terminate), surround, or otherwise =
affect the timing of signals carried by a net.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
The timing of signals on the net may be affected directly or indirectly =
by the above forms of energy, mechanics, and material properties. =
These parasitics may therefore include effects of coupling and \lquote =
over the cell\rquote routing.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Presumed, typical, or actual characteristics of the signals being =
carried (propagated) to the net through some port or via. Both static, =
steady state and transient signal characteristics may be prescribed.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Presumed, typical, or actual characteristics of the environment =
conditions, including, but not limited to, power, temperature, particle =
density, noise. Both static, steady state and transient =
characteristics may be prescribed.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Hierarchical structure of that portion of the design surrounding the =
net:
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Target net is assumed to be contained withi
n on block of an overall design hierarchy. The target net may also =
possibly be further contained within one layer or strata of the =
physically implemented design. Where a net consists of more than one =
net fragment (portion, net segment, subnet), the fragm
ents may be connected by a via or other intra-layer conducting =
mechanism.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Hierarchical driving boundary conditions: The signals carried by a net =
may pass from an upper level portion of the design hierarchy to the =
target net within a block by flowing from a
receiving instance port (occurrence port in the fully elaborated =
hierarchical design) \lquote down\rquote to the containing =
block\rquote=20
s interface definition port. Signals may also be carried from a lower =
level portion (sub-block or block instance) of the design hierarchy to =
the net by flowing \lquote up\rquote from a sub-block\rquote s driving =
instance port.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclistt=
ab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Hierarchical receiving boundary conditions: The signals are carried =
away from a net to some upper level portion of the design hierarchy =
from the target net within a block by flowing to the containing =
block\rquote s receiving interface definition port=20
\lquote up\rquote to the above portion of the design hierarchy. =
Signals may also be carried away from a net to some lower level portion =
of the design hierarchy by flowing \lquote down\rquote to a =
sub-block\rquote s receiving instance port.
\par {\pntext\pard\plain\f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\qj\fi-360\li360\sb120\nowidctlpar\widctlpar{\*\pn =
\pnlvlblt\ilvl0\ls3\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls3\adjustright \fs20\cgrid {
Hierarchical Boundary Parasitics Levels: are defined for several =
levels of detail, including=20
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright=20
\fs20\cgrid {high-level functional design parasitics constraints
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
logic design constraints
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Lumped parasitics generally applicable to 350nm and above
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Distributed R-C parasitics generally applicable t 250nm to 180nm
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Distributed R-L-C parasitics generally applicable to 180nm to perhaps =
around 130nm
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Distributed R-L-C-M parasitics generally applicable to 130nm to 100nm =
and below
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Hierarchical Parasitics
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
In CHDS, we are mov
ing to separate the representation of interconnect associated with the =
interface circuitry of the block from the interconnect associated with =
the internal definition of the block. The paradigm of separating =
interfacing effects from internal effects is we
ll known. The use of hierarchy, complex interface and interconnect =
parasitics, and the growing amount of coupling between nets gives rise =
to firm requirement to separate internal and interface interconnect =
effects in order to properly handle
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclistt=
ab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Interface interconnect is always instance and occurrence specific. The =
parasitics of the interface ports are likewise instance and occurrence =
specific.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Internal interconnect is always block definition specific. The =
parasitics of instance ports within the block\rquote s internal =
definition, once resolved with the instantiated lower-level circuitry, =
are normally constant with each block instance.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
External coupling or over-the-cell route coupling with internal =
interconnect requires treating the coupling-affected portion as part=20
of the interface interconnect. This is because the external coupling =
is by definition a form of interface access into the block definition.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
An interface port of a block (cell, macro, core) definition may =
normally be treated as two components: an open-circuit output (or =
input) impedance, and separately, the loaded incremental impedance,
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Open-Circuit (Unterminated) Impedance - Such open circuit impedance may =
be represented by a R-C, R-L-C, or R-L-C-M parasitic model of the =
interconnect interface circuitry \ldblquote behind\rdblquote=20
the interface port , including the effects of nets, vias, and =
net-to-net coupling. The parasitic model of the unloaded interface =
port is associated with the port
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
Loaded Incremental Impedance \endash the loaded incremental impedance =
may also be represented by a R-C, R-L-C, or R-L-C-M parasitic model of =
the interconnect instance port interface circuitry \ldblquote =
looking\rdblquote=20
into the interface port of the instantiated block.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
This should not include the parasitic model effects of the ports the =
drive or receive from the target port. Those effects are accounted for =
at those other ports.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\nowidctlpar\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls9\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls9\adjustright {
\par }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {\page <<< List of terms >>>
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\nowidctlpar\widctlpar\tx576\outlinelevel=
1\adjustright \b\cgrid {3.1\tab Functional Design Boundary Conditions
\par }\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\nowidctlpar\widctlpar\tx720\outlinelevel=
2\adjustright \b\cgrid {3.1.1\tab Fanout
\par }\pard\plain \s4\qj\fi-870\li870\sb120\keepn\nowidctlpar\widctlpar\=
tx870\outlinelevel3\adjustright \b\cgrid {3.1.1.1\tab Fanout Drive
\par }\pard =
\s4\qj\fi-864\li864\sb120\keepn\nowidctlpar\widctlpar\tx864\outlinelevel=
3\adjustright {Fanout Load
\par 3.1.1.2\tab Equivalent Fanin Loads
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\nowidctlpar\widctlpar\tx576\outlinelevel=
1\adjustright \b\cgrid {3.2\tab Logic Design Boundary Conditions
\par }\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\nowidctlpar\widctlpar\tx720\outlinelevel=
2\adjustright \b\cgrid {3.2.1\tab Drive Capability
\par }\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\nowidctlpar\widctlpar\tx864\outlinelevel=
3\adjustright \b\cgrid {Drive resistance
\par 3.2.1.1\tab Available Drive
\par 3.2.1.2\tab Equivalent Load
\par }\pard\plain \qj\sb120\nowidctlpar\widctlpar\adjustright =
\fs20\cgrid {
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\nowidctlpar\widctlpar\tx576\outlinelevel=
1\adjustright \b\cgrid {3.3\tab Lumped Parasitic Boundary Conditions
\par }\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\nowidctlpar\widctlpar\tx720\outlinelevel=
2\adjustright \b\cgrid {3.3.1\tab Effective Load Capacity
\par 3.3.2\tab Effective Load Resistance
\par 3.3.3\tab Effective Drive Capacitance
\par 3.3.4\tab Effective Drive Resistance
\par 3.3.5\tab Equivalent Custom Wire Load
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.6\tab}}\pard =
\s3\qj\fi-720\li720\sb120\keepn\nowidctlpar\widctlpar\jclisttab\tx720\ls=
10\ilvl2\outlinelevel2\adjustright {Equivalent Custom Wire =
Drive{\*\bkmkstart mark}{\*\bkmkend mark}

\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4\tab}}\pard\plain =
\s2\qj\fi-720\li720\sb240\keepn\nowidctlpar\widctlpar\tx576\jclisttab\tx=
720\ls10\ilvl1\outlinelevel1\adjustright \b\cgrid {Hierarchical =
boundary parasitics (impedance)=20
\endash for initial estimation of instantiating blocks, cells, and =
macros, and for later backannotated actual parasitics.
\par {\listtext\pard\plain\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.6\tab}}\pard\plain =
\qj\fi-720\li720\sb120\nowidctlpar\widctlpar\jclisttab\tx720\ls10\ilvl2\=
adjustright \fs20\cgrid {Unterminated (Open Circuit) Interface Port =
Parasitic (impedance) model

\par {\listtext\pard\plain\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.7\tab}Terminated (Loaded) Instance (Occurrence) Port Parasitic =
(impedance) model
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\nowidctlpar\widctlpar\tx576\outlinelevel=
1\adjustright \b\cgrid {3.5 Distributed R-C, R-L-C, and R-L-C-M =
Parasitic Boundary Conditions
\par }\pard =
\s2\qj\fi-570\li570\sb240\keepn\nowidctlpar\widctlpar\tx570\outlinelevel=
1\adjustright {3.7\tab Environment Boundary Conditions
\par }\pard =
\s2\qj\fi-576\li576\sb240\keepn\nowidctlpar\widctlpar\tx576\outlinelevel=
1\adjustright {On-chip or Overall Package Ambient Temperature
\par }\pard\plain \qj\sb120\nowidctlpar\widctlpar\adjustright =
\fs20\cgrid {\b Thermal Impedance=20
\par }\pard \qj\fi720\sb120\nowidctlpar\widctlpar\adjustright {\b chip =
over the packaging
\par block within the chip
\par leaf cell within a block
\par transistor within a cell, including local thermal characterics =
(static, steady-state, transient, peak, and RMS) of the channel, gate, =
source, and drain
\par }\pard \qj\sb120\nowidctlpar\widctlpar\adjustright {\b Power =
Dissipation \endash see above remarks on thermal}{
\par }{\b Process
\par \tab By name within the technology library
\par \tab Individual design-time applicable process characterisitcs, =
including nominal, average, min, max, statistical distribution, and =
correlation with both other process characterics and environment =
conditions
\par \page=20
\par }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Lumped RC parasitic model
\par }\pard\plain =
\s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {
Semantic definition: The distributed parasitic effects of a net or =
netsegment are represented by a single lumped value of capacitance and =
resistance. Nominal, best-case, and worst-
case RC value pairs may be specificed from which to calculate nominal, =
best-case, and/or worst-case net or netsegment delay, slew, and other =
related timing characteristics.
\par }{\b Type}{\tab Parasitic
\par }\pard\plain =
\s35\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Applies To}{\tab Hierarchical pins or =
primitive outputs
\par }\pard\plain =
\s33\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Depends On\tab }{process: Coefficient=20
\par }\pard\plain =
\s34\qj\li288\sb120\nowidctlpar\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain =
\s31\li288\sb120\sa120\nowidctlpar\widctlpar\adjustright \b\fs20\cgrid =
{Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb \cellx12599
\pard\plain \s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright =
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright=20
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1=20
\cltxlrtb \cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\nowidctlpar\widctlpar\adjustright {
\par }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: External load
\par }\pard\plain =
\s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {Semantic definition: An example portion of =
External Load would be the lumped capacitance that is or could be =
loading an output port or pin.

\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain =
\s34\qj\li288\sb120\nowidctlpar\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain =
\s31\li288\sb120\sa120\nowidctlpar\widctlpar\adjustright \b\fs20\cgrid =
{Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb \cellx12599
\pard\plain \s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright =
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright=20
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1=20
\cltxlrtb \cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: External Fanout=20
\par }\pard\plain =
\s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {Semantic definition: Identifies the number of =
effective loads (transistor circuits) lying behind an output port.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain =
\s34\qj\li288\sb120\nowidctlpar\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain =
\s31\li288\sb120\sa120\nowidctlpar\widctlpar\adjustright \b\fs20\cgrid =
{Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb \cellx12599
\pard\plain \s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright =
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright=20
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1=20
\cltxlrtb \cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: External Detailed Parasitics
\par }\pard\plain =
\s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {Semantic definition:=20
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain =
\s34\qj\li288\sb120\nowidctlpar\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain =
\s31\li288\sb120\sa120\nowidctlpar\widctlpar\adjustright \b\fs20\cgrid =
{Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb \cellx12599
\pard\plain \s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright =
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright=20
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1=20
\cltxlrtb \cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Driver Cell Type
\par }\pard\plain =
\s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {Semantic definition:=20
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain =
\s34\qj\li288\sb120\nowidctlpar\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain =
\s31\li288\sb120\sa120\nowidctlpar\widctlpar\adjustright \b\fs20\cgrid =
{Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb \cellx12599
\pard\plain \s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright =
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright=20
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1=20
\cltxlrtb \cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Drive Strength \endash }{\b0\i0 cell(s) input =
ports.
\par }\pard\plain =
\s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {Semantic definition:
Input ports: Identifies the amount of transistor circuit output =
capability available to drive in to an input port from some higher or =
lower level circuitry.
\par }\pard\plain =
\s30\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {Output ports: Identifies the amount of =
transistor circuit output capability available to drive o
ut through an output port to some higher or lower level circuitry.
\par }\pard\plain =
\s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain =
\s34\qj\li288\sb120\nowidctlpar\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain =
\s31\li288\sb120\sa120\nowidctlpar\widctlpar\adjustright \b\fs20\cgrid =
{Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb \cellx12599
\pard\plain \s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright =
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright=20
\fs20\cgrid {\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1=20
\cltxlrtb \cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain =
\s17\sb120\keep\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain =
\nowidctlpar\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\nowidctlpar\widctlpar\adjustright {
\par }\pard\plain \s25\qj\sb240\keepn\nowidctlpar\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Input Slew \endash }{\b0\i0=20
\par }\pard\plain \s28\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\t=
x6060\tx9390\adjustright \fs20\cf1\cgrid {Semantic definition: the =
time a signal flowing in through a port transistions from one digital =
level to another.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\nowidctlpar\widctlpar\tx1980\tx4620\tx6060\tx9390\adjus=
tright \fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain =
\s34\qj\li288\sb120\nowidctlpar\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain =
\s31\li288\sb120\sa120\nowidctlpar\widctlpar\adjustright \b\fs20\cgrid =
{Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
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Hierarchical Boundary Conditions
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Content-type: text/plain; name=taxonomy02sg.txt
Content-disposition: attachment; filename=taxonomy02sg.txt

Constraint Taxonomy
Version 0.2 - with Sgpass-1

Design Constraints Working Group

Open Verilog International

Virtual Socket Interface Alliance
Revision History

Revision
Date
Name
Comments
SGpass 1

0.2
7/6/98
Mark Hahn
Added a table of contents, clock
constraints, and did some reformatting
0.1
6/8/98
Mark Hahn
Initial Creation

Table Of Contents
1. Timing Domain 5
1.1 Clock Constraints 5
Clock 5
Specifies a set of points in the design at which a clock waveform originates 5
Clock Delay 6
Constraint on the timing characteristics of a clock network or a portion of a hierarchical clock
network 6
Clock Mode 8
Default for whether the ideal characteristics of clock networks should be used for analysis, or
whether the actual characteristics should be computed 8
Derived Waveform 9
A waveform which is derived from another waveform (by a clock multiplier or divider, for example) 9
Waveform 10
A description of an abstract waveform 10

1 Timing Domain

2 Exceptions
3 Parasitic Hierarchical Boundary Conditions
<<< ****************************************************************************
DCWG reviewers: This draft section is best described as being in 3 parts.
? A general discussion of parasitics from the point of view of external or interface ports of a
block definition and instance (potentially occurrence) ports of a block instance (boundary
conditions). I hope the terminology I use wont get in the way of your review, however, once
one goes fully hierarchical, then we have to become more specific than, for instance,
�external�. The discussion also covers the several levels of parasitics that are coming, e.g.,
distributed RC, RCL, and RCLM, all which need to include coupling.
? My current list of list of hierarchical parasitics at the boundaries of blocks in a design
hierarchy. I am in the process of redoing the appropriate ones to reflect those offer within the
Ambit synthesis constraints document.
? A first cut at fleshing the list of hierarchical parasitics at the boundaries of blocks in a design
hierarchy
************************************************************************** >>>
This section defines the Parasitic Hierarchical Boundary Conditions needed to define and constrain the
timing of signals being carried by a net and applicable operating environment conditions. These may be
defined from within the design descriptions and/or from tools and/or by the designer/user.
The scope of this section includes the following coverage and points of view:
? This section defines the boundary conditions that surround any particular net or fragment of a set within
a block within a design hierarchy. The boundary conditions therefore define the specific environment
for defining (prescribing) and/or constraining the timing of signals being carried by a net.
? Electrical, magnetic, optical, thermal, (and possibly other forms of energy), material, and mechanical
properties that drive (source, transmit), load (sink, receive, terminate), surround, or otherwise affect the
timing of signals carried by a net.
? The timing of signals on the net may be affected directly or indirectly by the above forms of energy,
mechanics, and material properties. These parasitics may therefore include effects of coupling and
�over the cell� routing.
? Presumed, typical, or actual characteristics of the signals being carried (propagated) to the net through
some port or via. Both static, steady state and transient signal characteristics may be prescribed.
? Presumed, typical, or actual characteristics of the environment conditions, including, but not limited to,
power, temperature, particle density, noise. Both static, steady state and transient characteristics may
be prescribed.
? Hierarchical structure of that portion of the design surrounding the net:
? Target net is assumed to be contained within on block of an overall design hierarchy. The target net
may also possibly be further contained within one layer or strata of the physically implemented design.
Where a net consists of more than one net fragment (portion, net segment, subnet), the fragments may
be connected by a via or other intra-layer conducting mechanism.
? Hierarchical driving boundary conditions: The signals carried by a net may pass from an upper level
portion of the design hierarchy to the target net within a block by flowing from a receiving instance
port (occurrence port in the fully elaborated hierarchical design) �down� to the containing block�s
interface definition port. Signals may also be carried from a lower level portion (sub-block or block
instance) of the design hierarchy to the net by flowing �up� from a sub-block�s driving instance port.
? Hierarchical receiving boundary conditions: The signals are carried away from a net to some upper
level portion of the design hierarchy from the target net within a block by flowing to the containing
block�s receiving interface definition port �up� to the above portion of the design hierarchy. Signals
may also be carried away from a net to some lower level portion of the design hierarchy by flowing
�down� to a sub-block�s receiving instance port.
? Hierarchical Boundary Parasitics Levels: are defined for several levels of detail, including
? high-level functional design parasitics constraints
? logic design constraints
? Lumped parasitics generally applicable to 350nm and above
? Distributed R-C parasitics generally applicable t 250nm to 180nm
? Distributed R-L-C parasitics generally applicable to 180nm to perhaps around 130nm
? Distributed R-L-C-M parasitics generally applicable to 130nm to 100nm and below
? Hierarchical Parasitics
? In CHDS, we are moving to separate the representation of interconnect associated with the interface
circuitry of the block from the interconnect associated with the internal definition of the block. The
paradigm of separating interfacing effects from internal effects is well known. The use of hierarchy,
complex interface and interconnect parasitics, and the growing amount of coupling between nets gives
rise to firm requirement to separate internal and interface interconnect effects in order to properly
handle
? Interface interconnect is always instance and occurrence specific. The parasitics of the interface ports
are likewise instance and occurrence specific.
? Internal interconnect is always block definition specific. The parasitics of instance ports within the
block�s internal definition, once resolved with the instantiated lower-level circuitry, are normally
constant with each block instance.
? External coupling or over-the-cell route coupling with internal interconnect requires treating the
coupling-affected portion as part of the interface interconnect. This is because the external coupling is
by definition a form of interface access into the block definition.
? An interface port of a block (cell, macro, core) definition may normally be treated as two components:
an open-circuit output (or input) impedance, and separately, the loaded incremental impedance,
? Open-Circuit (Unterminated) Impedance - Such open circuit impedance may be represented by a R-C,
R-L-C, or R-L-C-M parasitic model of the interconnect interface circuitry �behind� the interface port ,
including the effects of nets, vias, and net-to-net coupling. The parasitic model of the unloaded
interface port is associated with the port
? Loaded Incremental Impedance � the loaded incremental impedance may also be represented by a R-C,
R-L-C, or R-L-C-M parasitic model of the interconnect instance port interface circuitry �looking� into
the interface port of the instantiated block.
? This should not include the parasitic model effects of the ports the drive or receive from the target port.
Those effects are accounted for at those other ports.
?

<<< List of terms >>>
3.1 Functional Design Boundary Conditions
3.1.1 Fanout
3.1.1.1 Fanout Drive
Fanout Load
3.1.1.2 Equivalent Fanin Loads
3.2 Logic Design Boundary Conditions
3.2.1 Drive Capability
Drive resistance
3.2.1.1 Available Drive
3.2.1.2 Equivalent Load

3.3 Lumped Parasitic Boundary Conditions
3.3.1 Effective Load Capacity
3.3.2 Effective Load Resistance
3.3.3 Effective Drive Capacitance
3.3.4 Effective Drive Resistance
3.3.5 Equivalent Custom Wire Load
3.3.6 Equivalent Custom Wire Drive
3.4 Hierarchical boundary parasitics (impedance) � for initial estimation of
instantiating blocks, cells, and macros, and for later backannotated actual
parasitics.
3.4.6 Unterminated (Open Circuit) Interface Port Parasitic (impedance) model
3.4.7 Terminated (Loaded) Instance (Occurrence) Port Parasitic (impedance) model
3.5 Distributed R-C, R-L-C, and R-L-C-M Parasitic Boundary Conditions
3.7 Environment Boundary Conditions
On-chip or Overall Package Ambient Temperature
Thermal Impedance
chip over the packaging
block within the chip
leaf cell within a block
transistor within a cell, including local thermal characterics (static, steady-state, transient,
peak, and RMS) of the channel, gate, source, and drain
Power Dissipation � see above remarks on thermal
Process
By name within the technology library
Individual design-time applicable process characterisitcs, including nominal, average, min,
max, statistical distribution, and correlation with both other process characterics and environment
conditions

Name: Lumped RC parasitic model
Semantic definition: The distributed parasitic effects of a net or netsegment are represented by a single
lumped value of capacitance and resistance. Nominal, best-case, and worst-case RC value pairs may be
specificed from which to calculate nominal, best-case, and/or worst-case net or netsegment delay, slew,
and other related timing characteristics.
Type Parasitic
Applies To Hierarchical pins or primitive outputs
Depends On process: Coefficient
Verified By
Parameters
Name
Value Type
Restrictions
Semantics

Name: External load
Semantic definition: An example portion of External Load would be the lumped capacitance that is or
could be loading an output port or pin.
Type
Applies To
Depends On
Verified By
Parameters
Name
Value Type
Restrictions
Semantics

Name: External Fanout
Semantic definition: Identifies the number of effective loads (transistor circuits) lying behind an output
port.
Type
Applies To
Depends On
Verified By
Parameters
Name
Value Type
Restrictions
Semantics

Name: External Detailed Parasitics
Semantic definition:
Type
Applies To
Depends On
Verified By
Parameters
Name
Value Type
Restrictions
Semantics

Name: Driver Cell Type
Semantic definition:
Type
Applies To
Depends On
Verified By
Parameters
Name
Value Type
Restrictions
Semantics

Name: Drive Strength �cell(s) input ports.
Semantic definition: Input ports: Identifies the amount of transistor circuit output capability available to
drive in to an input port from some higher or lower level circuitry.
Output ports: Identifies the amount of transistor circuit output capability available to drive out through
an output port to some higher or lower level circuitry.
Type
Applies To
Depends On
Verified By
Parameters
Name
Value Type
Restrictions
Semantics

Name: Input Slew �
Semantic definition: the time a signal flowing in through a port transistions from one digital level to
another.
Type
Applies To
Depends On
Verified By
Parameters
Name
Value Type
Restrictions
Semantics

Timing Hierarchical Boundary Conditions

Constraint Taxonomy
07/21/98 Design Constraints Working Group 3

Constraint Taxonomy
07/21/98 Design Constraints Working Group 7

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