DC-WG: revised draft - hierarchical parasitic boundary conditions

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--Boundary_(ID_zDgewgRwhV0V4xTuJL1GTQ)
Content-type: text/plain

This draft has what I feel are a reasonably complete list of terms, but
is still incomplete in terms of creating the individual table entries.

--Steve Grout

--Boundary_(ID_zDgewgRwhV0V4xTuJL1GTQ)
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************************************************************************=
****
\par DCWG reviewers: This draft section is best =
described as being in 3 parts.
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A general discussion of parasitics from the point of view of external =
or interface ports of a block definition and instance (potentially =
occurrence) ports of a block instance (boundary conditions). I hope =
the terminology I use wont get in the way o
f your review, however, once one goes fully hierarchical, then we have =
to become more specific than, for instance, \lquote external\rquote=20
. The discussion also covers the several levels of parasitics that =
are coming, e.g., distributed RC, RCL, and RCLM, all which need to =
include coupling.
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My current list of list of hierarchical parasitics at the boundaries =
of blocks in a design hierarchy. I am in the process of redoing the =
appropriate ones to reflect those offer within the Ambit synthesis =
constraints document.
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\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
A first cut at fleshing the list of hierarchical parasitics at the =
boundaries of blocks in a design hierarchy
\par }\pard\plain \qj\sb120\widctlpar{\*\pn =
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************************************************************************=
** >>>
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c1011401b1011401b10118010c00000024030400a5011801a5011401
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05000000020101000000040000002d01060005000000090200000000
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0500000014022a8750c9050000000201010000000500000002010100
0000050000001402c202e800050000002e01010000001c000000320ac202e8000b000400=
000000000807b0046e6574206f72206e65745f6e170017000c000c00
17000e000c00170017000c001700050000002e0100000000050000001402000000000500=
000002010100000005000000020101000000040000002d0106000500
00001402f202fc00050000002e010100000016000000320af202fc000700040000000000=
0807b0047365676d656e746c1400170017002400170017000c000500
00002e010000000005000000140200000000040000002d01070005000000020101000000=
040000002701ffff040000002d010200040000002d01030007000000
1b04c5041a0521048e02040000002d010400040000002d010500030000001e0007000000=
1604a604de043f04ca02050000000201010000001c000000fb02bdff
00000000000090010000000004400022417269616c0000008a050a662182ed772a82ed77=
c067ef778a050a6600000a00040000002d0108000500000009020000
00000500000014024004ca02050000002e010100000023000000320a4004ca0210000400=
000000000807b00444657369676e2048696572617263687930002500
22000f0025002500130030000f002500160025001600220025002100050000002e010000=
00000500000014022a8750c91c000000fb028bff0000000000009001
0000000004400022417269616c00000026060a8f2182ed772a82ed77c067ef7726060a8f=
00000a00040000002d01090005000000020101000000040000002701ffff040000002d01=
0000030000000000}}}}}{
\par =
}}\dpx-40\dpy1056\dpxsize9029\dpysize6025\dpfillfgcr255\dpfillfgcg255\dp=
fillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat0\dplineh=
ollow}}}}{This section defines the Parasitic Hierarchical Boundary =
Condit
ions needed to define and constrain the timing of signals being carried =
by a net and applicable operating environment conditions. These may be =
defined from within the design descriptions and/or from tools and/or by =
the designer/user. }{
\revised\revauth2\revdttm103290353=20
\par }\pard \qj\sb120\widctlpar{\*\pn =
\pnlvlcont\ilvl0\ls0\pnrnot1\pndec }\pnrnot1\adjustright {
\par }\pard \qj\sb120\widctlpar{\*\pn =
\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\adjustright {The scope of this =
section includes the following coverage and points of view:=20
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc4\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr4\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
\fs20\cgrid {
This section defines the boundary conditions that surround any =
particular net or fragme
nt of a set within a block within a design hierarchy. The boundary =
conditions therefore define the specific environment for defining =
(prescribing) and/or constraining the timing of signals being carried =
by a net.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc5\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr5\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Electrical, magnetic, optical, thermal, (and possibly other forms of =
energy), material, and mechanical properties that drive (source, =
transmit), load (sink, receive, terminate), surround, or otherwise =
affect the timing of signals carried by a net.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc6\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr6\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{The t
iming of signals on the net may be affected directly or indirectly by =
the above forms of energy, mechanics, and material properties. These =
parasitics may therefore include effects of coupling and \lquote over =
the cell\rquote routing.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc7\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr7\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Presumed, typical, or actual ch
aracteristics of the signals being carried (propagated) to the net =
through some port or via. Both static, steady state and transient =
signal characteristics may be prescribed.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc8\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr8\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Presumed, typical, or actual characteristics of the environment =
conditions, including, but not limited to, power, temperature, particle =
density, noise. Both static, steady state and transient =
characteristics may be prescribed.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc9\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr9\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Hierarchical structure of
that portion of the design surrounding the net:
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc10\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr10\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Target net is assumed to be contained within =
on}{\revised\revauth2\revdttm103290261 e}{ block of an overall design =
hierarchy. The target net may=20
also possibly be further contained within one layer or strata of the =
physically implemented design. Where a net consists of more than one =
net fragment (portion, net segment, subnet), the fragments may be =
connected by a via or other intra-layer conducting
mechanism.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc11\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr11\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Hierarchical driving boundary conditions: The signals carried by a net =
may pass from an upper level portion of the design hierarchy to the =
target net within a block by flowing from a receiving instance port =
(occurrence port in the fully elaborated hierar
chical design) \lquote down\rquote to the containing block\rquote s =
interface definition port. Signals may also be carried from a lower =
level portion (sub-block or block instance) of the design hierarchy to =
the net by flowing \lquote up\rquote=20
from a sub-block\rquote s driving instance port.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc12\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr12\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Hierarchical receiving boundary conditions: The signals are carried =
away from a net to some upper level portion of the design hierarchy =
from the target net within a block by flowing to the containing =
block\rquote s receiving interface definition port=20
\lquote up\rquote to the above portion of the design hierarchy. =
Signals may also be carried away from a net to some lower level portion =
of the design hierarchy by flowing \lquote down\rquote to a =
sub-block\rquote s receiving instance port.
\par {\pntext\pard\plain\f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain \qj\fi-360\li360\sb120\widctlpar{\*\pn =
\pnlvlblt\ilvl0\ls6\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls6
\ls6\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrxs=
t240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\=
pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc1\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr1\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
\fs20\cgrid {
Hierarchical Boundary Parasitics Levels: are defined for several =
levels of detail, including=20
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc13\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr13\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
\fs20\cgrid {
high-level functional design parasitics constraints
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc14\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr14\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Logic design constraints
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc15\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr15\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Lumped parasitics }{
\revised\revauth2\revdttm103290264 - }{generally applicable to 350nm =
and above}{\revised\revauth2\revdttm103290265 . Coupling is via lumped =
capacitance}{\revised\revauth2\revdttm103290266 .}{
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc16\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr16\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Distributed R-C parasitics }{
\revised\revauth2\revdttm103290264 - }{generally applicable t 250nm to =
180nm}{\revised\revauth2\revdttm103290266 . Coupling is via =
distributed capacitance.}{
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc17\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr17\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Distributed R-L-C parasitics }{
\revised\revauth2\revdttm103290264 - }{generally applicable to 180nm to =
perhaps around 130nm}{\revised\revauth2\revdttm103290266 . Coupling is =
via distributed capacitance, with mutual coupling considered being =
negligible.}{
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc18\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr18\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Distributed R-L-C-M parasitics}{
\revised\revauth2\revdttm103290264 -}{ generally applicable to 130nm =
to 100nm and below}{\revised\revauth2\revdttm103290267 . Coupling is =
via distributed capacitance and distributed mutual inductance.}{
\par }\pard\plain \qj\sb120\widctlpar{\*\pn =
\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\adjustright \fs20\cgrid {\b =
Hierarchical }{\b\revised\revauth2\revdttm103290350 Boundary =
}{\b\deleted\revised\revauth2\revdttm103290350\revauthdel1\revdttmdel117=
7035314 a}{\b=20
Parasitics
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain \s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx3=
60{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc19\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr19\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
\fs20\cgrid {In CHDS}{
\revised\revauth2\revdttm103290270 and CHDStd}{, we are moving to =
separate the representation of interconnect =
}{\revised\revauth2\revdttm103290270 (and its parasitics) }{associated =
with the interface circuitry of the block from the }{
\revised\revauth2\revdttm103290270 representation of }{interconnect =
}{\revised\revauth2\revdttm103290271 (and its parasitics) }{associated =
with the internal definition of the block. The
paradigm of separating interfacing effects from internal effects is =
well known. The use of hierarchy, complex interface and internal =
interconnect parasitics, and the growing amount of coupling between =
nets are part of }{
\deleted\revauthdel2\revdttmdel103290271 our =
}{\revised\revauth2\revdttm103290271 the }{approach =
}{\revised\revauth2\revdttm103290271 needed }{to =
handl}{\revised\revauth2\revdttm103290271 =
e}{\deleted\revauthdel2\revdttmdel103290271 ing }{
the growing complexity at 180nm and below.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc20\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr20\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Interface interconnect is always instance and occurrence specific. The =
parasitics }{\revised\revauth2\revdttm103290272 of the interconnect and =
its surrounding drivers and loads that are reflected at =
}{\deleted\revauthdel2\revdttmdel103290273 of }{
the interface ports are likewise instance and occurrence specific.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc21\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr21\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Internal interconnect is always block_definition specific. The =
parasitics of instance ports within the block\rquote s internal =
definition, once resolved with the instantiated lower-level circuitry, =
are normally constant with each block instance.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc22\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr22\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
External coupling or over-the-cell route coupling with
internal interconnect requires treating the coupling-affected portion =
as part of the interface interconnect. This is because the external =
coupling is by definition a form of interface access into the block =
definition.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc23\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr23\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {An =
interface port of a block (cel
l, macro, core) definition may normally be treated as two components: =
an open-circuit output (or input) impedance, and separately, the loaded =
incremental impedance,
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc24\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr24\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
Open-Circuit (Unterminated) Impedance - Such open circuit impedance may =
be represented by a R-C, R-L-C, or R-L-C-M parasitic model of the =
interconnect interface circuitry \ldblquote behind\rdblquote=20
the interface port , including the effects of nets, vias, and =
net-to-net coupling. The parasitic model of the unloaded interface =
port is associated with the port
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc25\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr25\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Loaded }{
\revised\revauth2\revdttm103290274 (Terminated) }{Incremental Impedance =
\endash the loaded incremental impedance may also be represented by a =
R-C, R-L-C, or R-L-C-M parasitic model of the interconnect instance =
port interface circuitry \ldblquote looking
\rdblquote into the interface port of the instantiated block.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls12\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls12
\ls12\pnrauth2\pnrdate103290350\pnrstart0\pnrxst1\pnrxst0\pnrxst183\pnrx=
st240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0=
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnfc0\pnrnfc0\pnr=
nfc0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc26\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr26\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {
This should not include the parasitic model effects of the ports the =
drive or receive from the target port. Those effects are accounted for =
at those other ports.
\par }\pard\plain \qj\sb120\widctlpar
\qj\sb120\widctlpar\pnrauth2\pnrdate103290269\pnrstart0\pnrxst1\pnrxst0\=
pnrxst183\pnrxst240\pnrstop4\pnrstart1\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\p=
nrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc23\pnrnf=
c0\pnrnfc0\pnrnfc0\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc27\pnrnfc0\pnrnfc=
0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr27\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop3=
6\adjustright \fs20\cgrid {
\revised\revauth2\revdttm103290275 The above effects and requirements =
need to be reflected in the below list of hierarchical parasitic =
boundary conditions:}{
\par }\pard \qj\sb120\widctlpar\adjustright {\page =
}{\revised\revauth1\revdttm1177035315 The following are the proposed =
}{list of terms applicable to hierarchical parasitic boundary =
conditions:
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\tx576\outlinelevel1\adjustrigh=
t \b\cgrid {3.1\tab Functional Design Boundary Conditions
\par }\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\tx720\outlinelevel2\adjustrigh=
t \b\cgrid {3.1.1\tab Fanout
\par }\pard\plain =
\s4\qj\fi-870\li870\sb120\keepn\widctlpar\tx870\outlinelevel3\adjustrigh=
t \b\cgrid {3.1.1.1\tab Fanout Drive
\par }\pard =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\tx864\outlinelevel3\adjustrigh=
t {Fanout Load (Ambit)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {Fanout =
Load Limit (Ambit)
\par Equivalent External Sources (Ambit \endash num_external_sources)
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.1.2\tab}}\pard\plain \s4\qj\fi-870\li870\sb120\keepn\widctlpar\jclis=
ttab\tx870\ls14\ilvl3\outlinelevel3
\jclisttab\tx870\ls14\ilvl3\outlinelevel3\pnrauth2\pnrdate103290350\pnrs=
tart0\pnrxst7\pnrxst0\pnrxst0\pnrxst0\pnrxst46\pnrxst0\pnrxst1\pnrxst0\p=
nrxst46\pnrxst0\pnrxst2\pnrxst0\pnrxst46\pnrxst0\pnrxst3\pnrxst0\pnrstop=
16\pnrstart1\pnrrgb1\pnrrgb3
\pnrrgb5\pnrrgb7\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrsta=
rt2\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc1\pnrnfc0\pnrn=
fc0\pnrstop18\pnrstart3
\pnrpnbr3\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr1\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr1\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr2\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrstop36\adjustright \b\cgrid {Equivalent Fanin Loads
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid =
{Equivalent External Sinks (Ambit \endash num_external_sinks)
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\tx576\outlinelevel1\adjustrigh=
t \b\cgrid {3.2\tab Logic Design Boundary Conditions
\par }\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\tx720\outlinelevel2\adjustrigh=
t \b\cgrid {3.2.1\tab Drive =
Capability}{\revised\revauth2\revdttm103290278=20
\par }\pard\plain \qj\sb120\widctlpar\pnrnot1\adjustright \fs20\cgrid =
{Cell (Block) Drive (Ambit)
\par }\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\tx864\outlinelevel3\adjustrigh=
t \b\cgrid {Drive resistance (Ambit)
\par 3.2.1.1\tab Available Drive
\par 3.2.1.2\tab Equivalent Load
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\tx576\outlinelevel1\adjustrigh=
t \b\cgrid {3.3\tab Lumped Parasitic Boundary Conditions
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.1\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls16\ilvl2\out=
linelevel2
\jclisttab\tx720\ls16\ilvl2\outlinelevel2\pnrauth2\pnrdate103290350\pnrs=
tart0\pnrxst5\pnrxst0\pnrxst0\pnrxst0\pnrxst46\pnrxst0\pnrxst1\pnrxst0\p=
nrxst46\pnrxst0\pnrxst2\pnrxst0\pnrstop12\pnrstart1\pnrrgb1\pnrrgb3\pnrr=
gb5\pnrrgb0\pnrrgb0\pnrrgb0
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc0\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr3=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr3\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr1\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
\b\cgrid {Effective Load Capacity
\par }\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\tx864\outlinelevel3\adjustrigh=
t \b\cgrid {Port Capacitance
\par }\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\tx1008\outlinelevel4\adjustri=
ght \f1\fs22\cgrid {Input Port Capacitance (Ambit)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {Input =
Port Capacitance Limit (Ambit)
\par Output Port Capacitance (Ambit)
\par }\pard \qj\widctlpar\adjustright {Output Port Capacitance Limit =
(Ambit)
\par }\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\tx720\outlinelevel2\adjustrigh=
t \b\cgrid {3.3.2\tab Effective Load Resistance
\par 3.3.3\tab Effective Drive Capacitance
\par 3.3.4\tab Effective Drive Resistance
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.5\tab}}\pard =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls13\ilvl2\out=
linelevel2
\jclisttab\tx720\ls13\ilvl2\outlinelevel2\pnrauth2\pnrdate103290350\pnrs=
tart0\pnrxst5\pnrxst0\pnrxst0\pnrxst0\pnrxst46\pnrxst0\pnrxst1\pnrxst0\p=
nrxst46\pnrxst0\pnrxst2\pnrxst0\pnrstop12\pnrstart1\pnrrgb1\pnrrgb3\pnrr=
gb5\pnrrgb0\pnrrgb0\pnrrgb0
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc0\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr3=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr3\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr5\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
{Equivalent Custom Wire Load
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
While wire load models normally apply to the target net, during that =
portion of the design flow where wire load parasitics are being used, =
we will need also to encapsulate and store the effective amount of =
wireload model that is present at the hierarchica
l port or port instance.
\par Equivalent Custom Wire Load Mode (Ambit)
\par=20
\par Specified Wire Load Model (Ambit)
\par }\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\tx864\outlinelevel3\adjustrigh=
t \b\cgrid {Port Wire Load (Ambit)
\par }\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\tx1008\outlinelevel4\adjustri=
ght \f1\fs22\cgrid {Input Port Wire Load (Ambit)
\par Output Port Wire Load (Ambit)
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.6\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls13\ilvl2\out=
linelevel2
\jclisttab\tx720\ls13\ilvl2\outlinelevel2\pnrauth2\pnrdate103290350\pnrs=
tart0\pnrxst5\pnrxst0\pnrxst0\pnrxst0\pnrxst46\pnrxst0\pnrxst1\pnrxst0\p=
nrxst46\pnrxst0\pnrxst2\pnrxst0\pnrstop12\pnrstart1\pnrrgb1\pnrrgb3\pnrr=
gb5\pnrrgb0\pnrrgb0\pnrrgb0
\pnrrgb0\pnrrgb0\pnrrgb0\pnrstop9\pnrstart2\pnrnfc0\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr3=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr3\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr6\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright =
\b\cgrid {Equivalent Custom Wire Drive{\*\bkmkstart mark}{\*\bkmkend =
mark} - ???
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4\tab}}\pard\plain =
\s2\qj\fi-720\li720\sb240\keepn\widctlpar\tx576\jclisttab\tx720\ls13\ilv=
l1\outlinelevel1\adjustright \b\cgrid {Hierarchical boundary parasitics =
(impedance) \endash }{
Distributed R-C,R-L-C, and R-L-C-M Parasitic Boundary Conditions}{ for =
initial estimation of instantiating blocks, cells, and macros, and for =
later backannotated actual parasitics.
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {The =
below approach currently is being examined for applicability to fully =
accurate hierarchical net timing. The analysis and work todate =
indicates that a
t least of large number of nets may be accurately calculated from the =
below two port parasitic boundary conditions if the timing is then =
captured arc-wise in a timing view with also have both internal and =
interface timing arcs. An additional instanc
e-port incremental timing offset value is required at the \lquote =
edge\rquote of the timing view as part of representing the full =
instantiation of the hierarchical net parasitic model.
\par {\listtext\pard\plain\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.5\tab}}\pard =
\qj\fi-720\li720\sb120\widctlpar\jclisttab\tx720\ls13\ilvl2
\jclisttab\tx720\ls13\ilvl2\pnrauth2\pnrdate103290350\pnrstart0\pnrxst5\=
pnrxst0\pnrxst0\pnrxst0\pnrxst46\pnrxst0\pnrxst1\pnrxst0\pnrxst46\pnrxst=
0\pnrxst2\pnrxst0\pnrstop12\pnrstart1\pnrrgb1\pnrrgb3\pnrrgb5\pnrrgb0\pn=
rrgb0\pnrrgb0\pnrrgb0\pnrrgb0
\pnrrgb0\pnrstop9\pnrstart2\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc4\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr3\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr4\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr5\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {Unterminated (Open =
Circuit) Interface Port Parasitic (impedance) model \endash =
encapsulates the effects of the interface nets behind the port.
\par {\listtext\pard\plain\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.6\tab}}\pard =
\qj\fi-720\li720\sb120\widctlpar\jclisttab\tx720\ls13\ilvl2
\jclisttab\tx720\ls13\ilvl2\pnrauth2\pnrdate103290350\pnrstart0\pnrxst5\=
pnrxst0\pnrxst0\pnrxst0\pnrxst46\pnrxst0\pnrxst1\pnrxst0\pnrxst46\pnrxst=
0\pnrxst2\pnrxst0\pnrstop12\pnrstart1\pnrrgb1\pnrrgb3\pnrrgb5\pnrrgb0\pn=
rrgb0\pnrrgb0\pnrrgb0\pnrrgb0
\pnrrgb0\pnrstop9\pnrstart2\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc3\pnrnfc0\pnrnfc0\pnrn=
fc0\pnrnfc4\pnrnfc0\pnrnfc0\pnrstop18\pnrstart3\pnrpnbr3\pnrpnbr0\pnrpnb=
r0\pnrpnbr0\pnrpnbr4\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr6\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrstop36\adjustright {Terminated (Loaded) =
Instance (Occurrence) Port Parasitic (impedance) model \endash =
encapsulates the incremental effects of the interface nets as =
(potentially) lo
aded by the parasitics of the nets at the next level of the design =
hierarchy.
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\tx576\outlinelevel1
\tx576\outlinelevel1\pnrauth2\pnrdate103290350\pnrstart0\pnrxst3\pnrxst0=
\pnrxst0\pnrxst0\pnrxst46\pnrxst0\pnrxst1\pnrxst0\pnrstop8\pnrstart1\pnr=
rgb1\pnrrgb3\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnrrgb0\pnr=
stop9\pnrstart2\pnrnfc0
\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc0=
\pnrnfc0\pnrnfc3\pnrnfc0\pnrnfc0\pnrnfc0\pnrnfc7\pnrnfc0\pnrnfc0\pnrstop=
18\pnrstart3\pnrpnbr3\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr7\pnrpnbr0\pnrpn=
br0\pnrpnbr0\pnrpnbr0\pnrpnbr0
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0\pnrpnbr0=
\pnrpnbr0\pnrpnbr0\pnrstop36
\adjustright \b\cgrid {3.6 Environment Boundary Conditions
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid =
{Operating Conditions (Ambit)
\par }\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\tx576\outlinelevel1\adjustrigh=
t \b\cgrid {3.6.1 On-chip or Overall Package Ambient Temperature
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {\tab =
Ambient Temperation
\par \tab Chip Temperature
\par \tab Block/Cell Temperature
\par \tab Device Temperature
\par }{\b 3.6.2 Thermal Impedance=20
\par }\pard \qj\fi720\sb120\widctlpar\adjustright {\b chip over the =
packaging
\par }\pard \qj\sb120\widctlpar\adjustright {\tab }{\b block within the =
chip}{\b\revised\revauth2\revdttm103290336 }{\b =20
\par }\pard \qj\fi720\sb120\widctlpar\adjustright {\b leaf cell within =
a block
\par transistor within a cell, including local thermal characterics =
(static, steady-state, transient, peak, and RMS) of the channel, gate, =
source, and drain
\par }\pard \qj\sb120\widctlpar\adjustright {\b 3.6.3 Power =
Dissipation \endash see above remarks on thermal}{
\par }{\b 3.6.4 Process
\par \tab By name within the technology library
\par \tab Individual design-time applicable process characterisitcs, =
including nominal, average, min, max, statistical distribution, and =
correlation with both other process characterics and environment =
conditions
\par \page=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Lumped RC parasitic model
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: The distributed parasitic effects =
of a net or netsegment are represented by a single lumped value of =
capacitance and resi
stance. Nominal, best-case, and worst-case RC value pairs may be =
specificed from which to calculate nominal, best-case, and/or =
worst-case net or netsegment delay, slew, and other related timing =
characteristics.
\par }{\b Type}{\tab Parasitic
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Hierarchical pins or primitive =
outputs
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{process: Coefficient=20
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: External load
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: An example portion of External =
Load would be the lumped capacitance that is or could be loading an =
output port or pin.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: External Fanout=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Identifies the number of =
effective loads (transistor circuits) lying behind an output port.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: External Detailed Parasitics
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition:=20
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: Driver Cell Type
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition:=20
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: Drive Strength \endash }{\b0\i0=20
cell(s) input ports.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Input ports: Identif
ies the amount of transistor circuit output capability available to =
drive in to an input port from some higher or lower level circuitry.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Output ports: Identifies the amount of transistor =
circuit output capability available to drive out through an output p
ort to some higher or lower level circuitry.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Input Slew \endash }{\b0\i0=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: the time a signal flowing in =
through a port transistions from one digital level to another.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par }\pard\plain =
\s1\qj\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw3=
0\brsp20 \tx432\outlinelevel0\adjustright \b\fs28\kerning28\cgrid =
{\page {\*\bkmkstart _Toc422101857}Timing Hierarchical Boundary =
Conditions{\*\bkmkend _Toc422101857}

\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par=20
\par=20
\par }}

--Boundary_(ID_zDgewgRwhV0V4xTuJL1GTQ)
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