RE: DC-WG: Corrected Agenda for 9/29 teleconference

Steve.Grout@SEMATECH.Org
Tue, 29 Sep 1998 11:57:31 -0500

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Mark - Here is my current draft which has everything I have done
so far. Check to see if you can see the block diagram near the
opening of the chapter.

Regards,
--Steve

--Boundary_(ID_eQ+DBphY6ZN6Gm8Gop3MyA)
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Revision History}{
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\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 2\cell =
\cell Steve Grout\cell 2d pass list of objects, identify objects with =
Ambit C/L strawman de
finitions, copied in available Ambit definitions, and adding other =
definitions. Began to define both commands and design objects targeted =
by the commands.\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 1\cell =
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\endash discussion of requirements, first list of objects to be =
defined.\cell }\pard\plain=20
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\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {0.2\cell =
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\fs20\cf1\lang1024\cgrid {Specifies a set of points in the design at =
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of clock networks should be used for analysis, or whether the actual =
characteristics should be computed\tab=20
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{\lang1024 Derived Waveform\tab=20
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\fs20\cf1\lang1024\cgrid {A waveform which is derived from another =
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\par }\pard\plain \s38\li600\widctlpar\tqr\tx8640\adjustright \fs20\cf1\=
lang1024\cgrid {A description of an abstract waveform\tab=20
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}}\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\kerning28 =
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\hich\af0\dbch\af0\loch\f0 2\tab}}\pard\plain =
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parasitics}{\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 3\tab}Parasitic Hierarchical Boundary =
Conditions{\*\bkmkend _Toc422101856}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {<<< =
************************************************************************=
****
\par DCWG reviewers: This draft section is best =
described as being in 3 parts.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\fi-360\li1080\sb120\widctlpar\jclisttab\tx1080{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright \fs20\cgrid {
A general discussion of parasitics from the point
of view of external or interface ports of a block definition and =
instance (potentially occurrence) ports of a block instance (boundary =
conditions). I hope the terminology I use wont get in the way of your =
review, however, once one goes fully hierarchica
l, then we have to become more specific than, for instance, \lquote =
external\rquote . The discussion also covers the several levels of =
parasitics that are coming, e.g., distributed RC, RCL, and RCLM, all =
which need to include coupling.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
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\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
My current list of list of hierarchical parasitics at the boundaries =
of blocks in a design hierarchy. I am in the process of redoing the =
appropriate ones to reflect those offer within the Ambit synthesis =
constraints document.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\fi-360\li1080\sb120\widctlpar\jclisttab\tx1080{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
A first cut at fleshing the list of hierarchical parasitics at the =
boundaries of blocks in a design hierarchy
\par }\pard\plain \sb120\widctlpar{\*\pn =
\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\adjustright \fs20\cgrid { =
************************************************************************=
** >>>
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\par =
}}\dpx-40\dpy1056\dpxsize9029\dpysize6025\dpfillfgcr255\dpfillfgcg255\dp=
fillfgcb255\dpfillbgcr255\dpfillbgcg255\dpfillbgcb255\dpfillpat0\dplineh=
ollow}}}}{This section=20
defines the Parasitic Hierarchical Boundary Conditions needed to define =
and constrain the timing of signals being carried by a net and =
applicable operating environment conditions. These may be defined from =
within the design descriptions and/or from tools
and/or by the designer/user.=20
\par=20
\par The scope of this section includes the following coverage and =
points of view:=20
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright \fs20\cgrid {
This section defines the boundary conditions that surround any =
particular net or fragment of a set within a block within a design =
hierarchy. T
he boundary conditions therefore define the specific environment for =
defining (prescribing) and/or constraining the timing of signals being =
carried by a net.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Electrical, magnetic, optical, thermal, (and possibly other forms of =
energy), material, and mechanical properties that drive (source, =
transmit), load (sink, receive, terminate), surround, or otherwise =
affect the timing of signals carried by a net.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
The timing of signals on the net may be affected directly or indirectly =
by the above forms of energy, mechanics, and material properties. =
These parasitics may therefore include effects of coupling and \lquote =
over the cell\rquote routing.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Presumed, typical, or actual characteristics of the signals being =
carried (propagated) to the net through some port or via. Both static, =
steady state and transient signal characteristics may be prescribed.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Presumed, typical, or actual characteristics of the environment =
conditions, including, but not limited to, power, temperature, particle =
density, noise. Both static, steady state and transient =
characteristics may be prescribed.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Hierarchical structure of that portion of the design surrounding the =
net:
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {Target net is assume
d to be contained within one block of an overall design hierarchy. The =
target net may also possibly be further contained within one layer or =
strata of the physically implemented design. Where a net consists of =
more than one net fragment (portion, net seg
ment, subnet), the fragments may be connected by a via or other =
intra-layer conducting mechanism.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Hierarchical driving boundary conditions: The signals carried by a net =
may pass from an upper level portion of the design hierarchy to the =
target net withi
n a block by flowing from a receiving instance port (occurrence port in =
the fully elaborated hierarchical design) \lquote down\rquote to the =
containing block\rquote=20
s interface definition port. Signals may also be carried from a lower =
level portion (sub-block or block instance) of the design hierarchy to =
the net by flowing \lquote up\rquote from a sub-block\rquote s driving =
instance port.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Hierarchical receiving boundary conditions: The signals are carried =
away from a net to some upper level portion of the design hierarchy =
from the target net within a block by flowing to the containing =
block\rquote s receiving interface definition port=20
\lquote up\rquote to the above portion of the design hierarchy. =
Signals may also be carried away from a net to some lower level portion =
of the design hierarchy by flowing \lquote down\rquote to a =
sub-block\rquote s receiving instance port.
\par {\pntext\pard\plain\f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain \fi-360\li360\sb120\widctlpar{\*\pn =
\pnlvlblt\ilvl0\ls13\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls13\adjustright \fs20\cgrid {
Hierarchical Boundary Parasitics Levels: are defined for several =
levels of detail (aka levels of abstraction), including the following:
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright \fs20\cgrid {
High-level functional design parasitics boundary conditions
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {Logic des
ign parasitic boundary conditions
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {constraints
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Lumped parasitics - generally applicable to 350nm and above. Coupling =
is via lumped capacitance. (This is the level of detail currently in =
wide spread use.)
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Distributed R-C parasitics - generally applicable t 250nm to 180nm. =
Coupling is via distributed capacitance. (This is the level of detail =
just coming into wide spread practice.)
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Distributed R-L-C parasitics - generally applicable to 180nm to perhaps =
around 130nm. Coupling is via distributed capacitance, with mutual =
coupling considered being negligible.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li720\sb120\widctlpar\jclisttab\tx720{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Distributed R-L-C-M parasitics - generally applicable to 130nm to 100nm =
and below. Coupling is via distributed capacitance and distributed =
mutual inductance.
\par }\pard\plain \sb120\widctlpar{\*\pn =
\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\adjustright \fs20\cgrid {\b =
Hierarchical Boundary Parasitics
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright \fs20\cgrid {
In CHDS and CHDStd, we are moving to separate the representation of =
interconnect (and its parasitics) associated with the interface =
circuitry of the block from the representation of interconnect (and its =
parasitics) associated with the internal defi
nition of the block. The paradigm of separating interfacing effects =
from internal effects is well known. The use of hierarchy, complex =
interface and internal interconnect parasitics, and the growing amount =
of coupling between nets are part of the approa
ch needed to handlethe growing complexity at 180nm and below.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Interface interconnect is always instance and occurrence specific. The =
parasitics of the interconnect and its surrounding drivers and loads =
that are reflected at the interface ports are likewise instance and =
occurrence specific.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Internal interconnect is always block_definition specific. The =
parasitics of instance ports within the block\rquote s internal =
definition, once resolved with the instantiated lower-level circuitry, =
are normally constant with each block instance.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
External coupling or over-the-cell route coupling with internal =
interconnect requires treating the coupling-affected portion as part of =
the interface interconnect. This is because the external coupling is =
by definition a form o
f interface access into the block definition.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
An interface port of a block (cell, macro, core) definition may =
normally be treated as two components: an open-circuit output (or =
input) impedance, and separately, the loaded incremental impedance,
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {Open-C
ircuit (Unterminated) Impedance - Such open circuit impedance may be =
represented by a R-C, R-L-C, or R-L-C-M parasitic model of the =
interconnect interface circuitry \ldblquote behind\rdblquote=20
the interface port , including the effects of nets, vias, and =
net-to-net coupling. The parasitic model of the unloaded interface =
port is associated with the port
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
Loaded (Terminated) Incremental Impedance \endash the loaded =
incremental impedance may also be represented by a R-C, R-L-C, or =
R-L-C-M parasitic model of the interconnect instance port interface =
circuitry \ldblquote looking\rdblquote=20
into the interface port of the instantiated block.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard \s44\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {
This should not include the parasitic model effects of the ports the =
drive or receive from the target port. Those effects are accounted for =
at those other ports.
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {The above =
effects and requirements need to be reflected in the below list of =
hierarchical parasitic boundary conditions:
\par \page The following are the proposed list of terms for =
hierarchical parasitic boundary conditions:
\par {\*\bkmkstart mark}{\*\bkmkend mark}{\listtext\pard\plain\s2 =
\b\fs20\cgrid \hich\af0\dbch\af0\loch\f0 3.1\tab}}\pard\plain =
\s2\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls27\ilvl1\outlin=
elevel1\adjustright \b\cgrid {\fs20=20
Functional Design Boundary Conditions
\par {\listtext\pard\plain\s3 \b\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.1\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls27\ilvl2\outlin=
elevel2\adjustright \b\cgrid {\fs20 Fanout
\par {\listtext\pard\plain\s4 \b\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.1.1\tab}}\pard\plain =
\s4\fi-870\li870\sb120\keepn\widctlpar\tx870\ls27\ilvl3\outlinelevel3\ad=
justright \b\cgrid {\fs20 Fanout Drive
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.1.2\tab}}\pard\plain =
\s3\fi-780\li780\sb120\keepn\widctlpar\jclisttab\tx780\ls26\ilvl3\outlin=
elevel2\adjustright \b\cgrid {Fanout Load (Ambit)
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\fs18\cf1\cgrid0 Ambit Command:}{\f16\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_fanout_load
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 =
Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 set_fanout_load <load> <port_list>
\par }{\b\fs18\cf1\cgrid0 Ambit Description:}{\i\fs18\cgrid0 }{\cgrid0 =
The }{\f6\fs16\cgrid0 set_fanout_load }{\cgrid0=20
command is used to specify the fanout load on the ports of a cell. =
While port capacitance affects timing analysis, fanout loads are used =
to enforce the design rule checks.
\par }{\b\fs18\cf1\cgrid0 DCWG Description:}{\cgrid0 }{\f6\fs16\cgrid0 =
fanout_load: }{\cgrid0 Specifies the expected or budgeted fanout load =
on the
ports of a cell when the cell is instantiated. While port capacitance =
affects timing analysis, fanout loads are used during planning the =
loading of a cell, and later to enforce the design rule checks of the =
application or use a cell.
\par }{\b\cgrid0 Arguments:}{\cgrid0=20
\par }\pard \fi720\sb120\widctlpar\adjustright {\cgrid0 Ambit =
Arguments:
\par }\pard \fi720\li720\sb120\widctlpar\adjustright {\cgrid0 =
Load;}{\i\f17\cgrid0 }{\f1\fs18\cgrid0 Total fanout load external to =
the cell.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f17\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 List of ports.}{\f1\fs18\cgrid0=20
\par }\pard \fi720\sb120\widctlpar\adjustright {\cgrid0 DCWG =
Load;}{\i\f17\cgrid0 }{\f1\fs18\cgrid0 Total fanout load external to =
the cell.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f17\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 List of ports.}{\f1\fs18\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
}{\f6\fs16\cgrid0 None
\par }\pard \widctlpar\adjustright {\b\cgrid0 Attributes:}{\cgrid0 =
fanout_load_limit
\par }{\b\cgrid0 Design Database:}{\cgrid0 =20
\par }\pard \nowidctlpar\adjustright {\b Related =
Commands}{\b\f1\fs18\cf1\cgrid0 :}{\f1\fs18\cf1\cgrid0 =
set_current_module
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.1.2\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Fanout Load Limit (Ambit)
\par {\listtext\pard\plain\s5 \b\fs22 \hich\af0\dbch\af0\loch\f0 =
3.1.1.2.1\tab}}\pard\plain =
\s5\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\outl=
inelevel4\adjustright \b\fs22\cgrid {\cgrid0 set_fanout_load_limit
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\fs18\cf1\cgrid0 Command:}{\f16\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Syntax:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit <load port_list>
\par }\pard \sb120\nowidctlpar\adjustright {\b\cf1\cgrid0 =
Description:}{\cf1\cgrid0 The set_fanout_load_limit command is used to =
specify the fanout load limit (
maximum value) on the ports of a cell. While port capacitance affects =
timing analysis, fanout loads are used to enforce the design rule =
checks. The design rule requirement of a maximum fanout load value is =
set using the global attribute fanout_load_limit.
=20
\par }{\f16\cf1\cgrid0 This command overrides the default fanout load =
limit on specific ports set by the global attribute =
}{\f6\fs16\cf1\cgrid0 fanout_load_limit}{\f16\cf1\cgrid0 .
\par }{\b\fs18\cf1\cgrid0 Arguments:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 load }{\i\f17\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 Fanout load limit on the ports.
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f17\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Options:}{\f1\fs18\cf1\cgrid0 None
\par }{\b\fs18\cf1\cgrid0 Attributes:}{\f1\fs18\cf1\cgrid0 =
fanout_load_limit
\par }{\b\fs18\cf1\cgrid0 Design Database:
\par Related Commands:}{\f1\fs18\cf1\cgrid0 set_current_module, =
set_fanout_load
\par }{\b\fs18\cf1\cgrid0 Examples:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_fanout_load_limit 4 [find -port -output =
data*]}{\f16\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.1.3\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls27\ilvl3\outlinelevel3\adjustright \b\cgrid {External Fanout=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Identifies the number of =
effective loads (transistor circuits) lying behind an output port.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.2\tab}}\pard\plain \s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\=
tx720\jclisttab\tx780\ls27\ilvl2\outlinelevel2\adjustright \b\cgrid =
{Equivalent External Sources (Ambit \endash=20
num_external_sources)
\par {\listtext\pard\plain\s4 \b \hich\af0\dbch\af0\loch\f0 =
3.1.2.1\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls27\ilvl3\outlinelevel3\adjustright \b\cgrid {\cgrid0 =
set_num_external_sources
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f16\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 =
set_num_external_sources
\par }{\b\cf1\cgrid0 Syntax: }{\cf1\cgrid0 set_num_external_sources =
<num_sources> <port_list>
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 Description: =
}{\cf1\cgrid0=20
The set_num_external_sources command can be specified on top level =
input and output ports. This command sets the constraint that the =
number of external sources specified by the command
are connected to the ports in the port list. This number is factored =
into the wire capacitance and wire resistance estimation done for the =
port nets using the wire load models.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f1\fs18\cf1\cgrid0 num_sources \emdash Number of external sources
\par }\pard \sb120\nowidctlpar\adjustright {\f1\fs18\cf1\cgrid0 =
port_list \emdash List of ports
\par }\pard\plain \s18\nowidctlpar\adjustright \b\f4\fs20\cf1\cgrid =
{\f0\cgrid0 Options:
\par Attributes:
\par Design Database:
\par Related Commands:
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\b\cf1\cgrid0 =
Examples:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs18\cf1\cgrid0 =
set_num_external_sinks
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs18\cf1\cgrid0 =
set_port_capacitance
\par do_derive_context
\par do_time_budget}{\f16\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.3\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Fanin}{\fs20=20
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.3.1\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Equivalent Fanin Loads
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.3.2\tab}}\pard =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx864\ls27\ilvl3\outlin=
elevel3\adjustright {Equivalent External Sinks (Ambit \endash =
num_external_sinks)
\par {\listtext\pard\plain\s5 \b\fs22 \hich\af0\dbch\af0\loch\f0 =
3.1.3.2.1\tab}}\pard\plain =
\s5\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\outl=
inelevel4\adjustright \b\fs22\cgrid {\cgrid0 set_num_external_sinks
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f16\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 =
set_num_external_sinks
\par }{\b\cf1\cgrid0 Syntax:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_num_external_sinks <num_sinks> <port_list>
\par }{\b\cf1\cgrid0 Description: }{\cf1\cgrid0 The =
set_num_external_sinks command can be specified on top level input and =
output ports. This command sets the constraint t
hat the number of external sinks specified by the command are connected =
to the ports in the port list. This number is factored into the wire =
capacitance and the wire resistance estimation done for the port nets =
using the wire load models. It does not add
towards the total fanout count for Design Rule Violation (DRV).=20
\par If you do not annotate set_num_external_sinks, then the fanout is =
1 for the port (and any other internal sinks of the wire). If you =
specify set_num_external_sinks, then you get that exact nu
mber added to the count of internal sinks of the wire. Therefore, =
setting set_num_external_sinks 1 has no effect.
\par For more information on design rule violations, see the =
description for \ldblquote set_fanout_load\rdblquote .
\par }{\b\cf1\cgrid0 Arguments}{\b\f1\fs18\cf1\cgrid0 : =
}{\f6\fs16\cf1\cgrid0 num_sinks }{\f1\fs18\cf1\cgrid0 \emdash Number =
of external sinks
\par }{\f6\fs16\cf1\cgrid0 port_list }{\f1\fs18\cf1\cgrid0 \emdash =
List of ports
\par }{\b\cf1\cgrid0 Options:
\par }{\f1\fs18\cf1\cgrid0 Attributes
\par }{\b\cf1\cgrid0 Design Database:=20
\par Related Commands:}{\b\f1\fs18\cf1\cgrid0 }{\f1\fs18\cf1\cgrid0 =
set_num_external_sources, set_port_capacitance, do_derive_context, =
do_time_budget, set_port_wire_load, set_fanout_load
\par }{\b\cf1\cgrid0 Examples:
\par }{\f16\fs16\cf1\cgrid0=20
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.1.3.3\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls27\ilvl3\outlinelevel3\adjustright \b\cgrid {External load
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: An example portion of External =
Load would be the lumped capacitance that is or could be loading an =
output port or pin.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\nowidctlpar\adjustright {\f16\fs16\cf1\cgrid0=20
\par=20
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2\tab}}\pard\plain =
\s2\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls27\ilvl1\outlin=
elevel1\adjustright \b\cgrid {Logic Design Boundary Conditions
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls27\ilvl2\outlin=
elevel2\adjustright \b\cgrid {Drive Capability
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1.1\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx864\ls27\ilvl3\outlin=
elevel3\adjustright \b\cgrid {Cell (Block) Drive (Ambit)
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1.2\tab}Drive resistance (Ambit)
\par {\listtext\pard\plain\s5 \b\fs22 \hich\af0\dbch\af0\loch\f0 =
3.2.1.2.1\tab}}\pard\plain =
\s5\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\outl=
inelevel4\adjustright \b\fs22\cgrid {\cgrid0 set_drive_resistance
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f16\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 set_drive_resistance
\par }{\b\cf1\cgrid0 Syntax:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_drive_resistance ?-rise | -fall? ?-early | =
-late? value
\par port_list
\par }{\b\cf1\cgrid0 Description: }{\cf1\cgrid0=20
The set_drive_resistance command is a simpler version of the =
set_drive_cell command and can be used in many situations where the =
drive resistance can be specified. It is only used for timing analysis. =
It does not affect the electrical p
roperties of the design. It is used to specify the drive resistance of =
a cell. It computes an offset to the arrival time of an input and also =
changes the slew time used to compute the delay of the cell on the sink =
of the net.
\par The arrival time at the input=20
port is modified by adding the RC constant to the specified arrival =
time at the input port. The RC constant is the capacitance(C) seen at =
the input port multiplied by the drive resistance (R). The RC value is =
used as the slew value for the delay calculati
on of the next cell. This command overrides the set_drive_cell command =
per port if it is the last command applied. Also, if =
set_drive_resistance is set for a port, set_slew_time is ignored for =
that port.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 value }{\i\f17\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 Resistance value.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f17\cf1\cgrid0 \emdash =
}{\f16\cf1\cgrid0 List of ports for which drive resistance is =
specified.
\par }{\b\f1\fs18\cf1\cgrid0 Options: }{\f1\fs18\cf1\cgrid0 =
-}{\f6\fs16\cf1\cgrid0 rise \emdash }{\f1\fs18\cf1\cgrid0 Specifies =
that the drive resistance is applicable to only the rising edge =
transition at the input port.
\par -}{\f6\fs16\cf1\cgrid0 fall \emdash }{\f1\fs18\cf1\cgrid0 =
Specifies that the resistance is applicable only to the falling edge =
transition at the input port. If either }{\f6\fs16\cf1\cgrid0 rise =
}{\f1\fs18\cf1\cgrid0 nor }{\f6\fs16\cf1\cgrid0 fall }{
\f1\fs18\cf1\cgrid0 options are specified then the resistance is =
applied to both transitions at the input port.
\par -}{\f6\fs16\cf1\cgrid0 early \emdash }{\f1\fs18\cf1\cgrid0 =
Specifies that the drive resistance should be applied to the early =
arrival time (hold time) for timing analysis.
\par }{\f16\cf1\cgrid0 -}{\f6\fs16\cf1\cgrid0 late \emdash =
}{\f1\fs18\cf1\cgrid0 Specifies that the drive resistance should be =
applied to the late arrival time (setup time) for timing =
analysis}{\f16\cf1\cgrid0 .
\par }{\f1\fs18\cf1\cgrid0 Attributes
\par }{\b\f1\fs18\cf1\cgrid0 Design Database: }{\f1\fs18\cf1\cgrid0=20
\par }{\b\f1\fs18\cf1\cgrid0 Related Commands: }{\f1\fs18\cf1\cgrid0 =
set_drive_cell
\par set_slew_time
\par }{\b\f1\fs18\cf1\cgrid0 Examples: }{\f6\fs16\cf1\cgrid0 =
set_drive_resistance=20
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
[expr 3 * [get_cell_drive -cell IV \endash pin A] ] [-input -port * =
]}{\f16\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1.3\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx864\ls27\ilvl3\outlin=
elevel3\adjustright \b\cgrid {Available Drive
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1.4\tab}}\pard =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls27\ilvl3\outlinelevel3\adjustright {Drive Strength \endash cell(s) =
input ports.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition:=20
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1.4.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Input ports: =20
\par }\pard\plain \qj\widctlpar\adjustright \fs20\cgrid {Identifies the =
amount of transistor circuit output capability available to drive in to =
an input port from some higher or lower level circuitry.
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1.4.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Output ports: =20
\par }\pard\plain \qj\widctlpar\adjustright \fs20\cgrid {pIdentifies =
the amount of transistor circuit output capability available to drive =
out through an output port to some higher or lower level circuitry.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\widctlpar\adjustright {
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.2.1.5\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx864\ls27\ilvl3\outlin=
elevel3\adjustright \b\cgrid {Equivalent Load
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3\tab}}\pard\plain =
\s2\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls27\ilvl1\outlin=
elevel1\adjustright \b\cgrid {Lumped Parasitic Boundary Conditions
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.1\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Effective Load Capacity
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.2\tab}Port Capacitance
\par {\listtext\pard\plain\s4 \b \hich\af0\dbch\af0\loch\f0 =
3.3.2.1\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx864\ls27\ilvl3\outlin=
elevel3\adjustright \b\cgrid {\cgrid0 set_port_capacitance }{\fs20 =
(Ambit)}{\cgrid0=20
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f16\cf1\cgrid0 Command}{\f16\cf1\cgrid0 : }{\f6\fs16\cf1\cgrid0 =
set_port_capacitance
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 =
Syntax:}{\b\f1\fs18\cgrid0 :}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance <capacitance> <port_list>
\par }{\b\cgrid0 Description: }{\cgrid0 The }{\f6\fs16\cgrid0 =
set_port_capacitance }{\cgrid0 command specifies the capacitance =
external to the design based on input and output loading from other =
ports and nets connected to the ports of the current module.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {\cgrid0 =
The capacitance at any port is the sum of the external port =
capacitances the port is connecte
d to. For an input port the port capacitance refers to the capacitance =
of all the ports of the driver that are connected to the net and the =
capacitance of the other loads on the net. For output ports, the port =
capacitance refers to the capacitance of all=20
the external sinks, or external drivers, for the case of =
multiply-driven net, that are connected to the net as well as the =
capacitance of the input port of any other external drivers
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Arguments: =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f17\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par port_list }{\i\f17\cgrid0 \emdash }{\f1\fs18\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
None
\par }{\b\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb240\widctlpar\adjustright {\b\cgrid0 Design Database: =
}{\cgrid0 None
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_current_module, set_port_capacitance_limit
\par }{\b\cgrid0 Examples: }{\cgrid0 This command sets a 3.2 =
capacitance on all output ports of the current module whose names match =
dbus at the start The unit of capacitance will be the same as the unit =
of capacitance used in the library.
\par }\pard \fi720\sb120\widctlpar\adjustright {\f2\cgrid0 =
set_port_capacitance 3.2 [find -port \endash output }{\f2\cf1\cgrid0 =
bus*]
\par {\listtext\pard\plain\s5 \b\fs22 \hich\af0\dbch\af0\loch\f0 =
3.3.2.1.1\tab}}\pard\plain =
\s5\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\outl=
inelevel4\adjustright \b\fs22\cgrid {\cgrid0 set_port_capacitance_limit =
}{\fs20 (Ambit)}{
\cgrid0=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
{\b\f16\cgrid0 Command:}{\f16\cgrid0 }{\cgrid0 =
set_port_capacitance_limit
\par }{\b\fs18\cgrid0 Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance_limit <capacitance> <port_list>
\par }{\b\fs18\cgrid0 Description:}{\cgrid0 The }{\fs16\cgrid0 =
set_port_capacitance_limit }{\cgrid0 command specifies the limit on the =
}{\fs18\cgrid0 capacitance}{\cgrid0 (maximum value) external to the =
design based on input }{\fs18\cf1\cgrid0=20
and output loading from other ports and nets connected to the ports of =
the current module. }{\cf1\cgrid0 It is used to override design rule =
constraints set by the global attribute
\par }{\b\fs18\cgrid0 set_capacitance_limit:}{\cgrid0 These =
constraints can be specified on top }{\f16\cf1\cgrid0 level input and =
output ports. It sets the constraint that the total capacitances
(i.e wire capacitance nd pin capacitance) of nets attached to the =
ports in the port list do not exceed the specified capacitance limit. =
This command overrides the default limit set by the =
}{\f6\fs16\cf1\cgrid0 set_global_capacitance_limit }{
\f16\cf1\cgrid0 command}{\f1\fs18\cf1\cgrid0 .
\par }{\b\fs18\cgrid0 Arguments:}{\cgrid0 =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f17\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f17\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\fs18\cgrid0 =
Options:}{\cgrid0 None
\par }{\b\fs18\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb120\nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_fanout_load_limit, }{\f1\fs18\cf1\cgrid0=20
set_slew_limit, set_port_capacitance, set_num_external_sources, =
set_num_external_sinks, do_derive_context, do_time_budget, set_global =
capacitance_limit
\par }{\b\cgrid0 Examples:}{\f1\cgrid0 }{\cgrid0 =
set_port_capacitance_limit 5.0 [find -port dbus*]
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.2.2\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx864\ls27\ilvl3\outlin=
elevel3\adjustright \b\cgrid {Input Port Capacitance=20
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\f16\fs16\cf1\cgrid0=20
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.2.2.1\tab}}\pard\plain =
\s5\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\outl=
inelevel4\adjustright \b\fs22\cgrid {Input Port Capacitance Limit=20
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\f16\fs16\cf1\cgrid0=20
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.2.3\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx864\ls27\ilvl3\outlin=
elevel3\adjustright \b\cgrid {Output Port Capacitance=20
\par }\pard\plain \widctlpar\adjustright \fs20\cgrid {
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.2.3.1\tab}}\pard\plain =
\s5\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\outl=
inelevel4\adjustright \b\fs22\cgrid {Output Port Capacitance Limit=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.3\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Effective Load Resistance
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.4\tab}Effective Drive Capacitance
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.5\tab}Effective Drive Resistance
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.6\tab}Equivalent Custom Wire Load
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
While wire load models normally apply to the target net, during that =
portion of the design flow where wire load parasitics are being used, =
we will need also to encapsulate and store the effective amount of =
wireload model that is present at the hierarchica
l port or port instance.
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.6.1\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Equivalent Custom Wire =
Load Mode (Ambit)
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.6.2\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Specified Wire Load Model =
(Ambit)
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.7\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Port Wire Load (Ambit)
\par {\listtext\pard\plain\s4 \b \hich\af0\dbch\af0\loch\f0 =
3.3.7.1\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {\cgrid0 =
set_port_wire_load
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Command:}{\f16\cgrid0 }{\cgrid0 set_port_wire_load
\par }\pard \widctlpar\adjustright {\b\cgrid0 Syntax:}{\f1\fs18\cgrid0 =
}{\cgrid0 set_port_wire_load ?-library <library_name>? <wire_load> =
}{\f6\fs16\cf1\cgrid0 <port_list>
\par }{\b\cgrid0 Description:}{\cgrid0 }{ }{\cgrid0 The =
set_port_wire_load command specifies the wire load for either =
}{\cf1\cgrid0=20
an input or output top level port of a design. The net connected to the =
port is associated with the specified wire load model, which is used =
for wire cap
and resistance estimation. If a net is connected to more than one port =
with a set_port_wire_load assertion, then the worst wire load model is =
computed and used for the net. The library name indicates the location =
of the specified wire load model. If the=20
library is not specified, then the wire load is located from the target =
technology (the default location).
\par }{\b\cgrid0 Arguments:}{\cgrid0=20
\par }{\b\cgrid0 Options:}{\cgrid0=20
\par }{\b\cgrid0 Attributes:}{\cgrid0=20
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par Related Commands:}{\f1\fs18\cf1\cgrid0 set_wire_load, =
set_num_external_sinks
\par }{\b\fs18\cf1\cgrid0 Examples:
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.7.2\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Input Port Wire Load =
(Ambit)
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {See =
set_port_wire_load.
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.7.3\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Output Port Wire Load =
(Ambit)
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {See =
set_port_wire_load.
\par=20
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.7.4\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Equivalent Custom Wire =
Drive - ???
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.3.8\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Lumped RC parasitic model
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b Semantic =
definition:}{ The distributed parasitic effects of a net or netsegment =
are represen
ted by a single lumped value of capacitance and resistance. Nominal, =
best-case, and worst-case RC value pairs may be specificed from which =
to calculate nominal, best-case, and/or worst-case net or netsegment =
delay, slew, and other related timing characte
ristics.
\par }{\b Type:}{\tab Parasitic
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To:}{\tab Hierarchical pins or primitive =
outputs
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On:\tab }{process: Coefficient=20
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By:}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {
\par=20
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4\tab}}\pard\plain =
\s2\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls27\ilvl1\outlin=
elevel1\adjustright \b\cgrid {Distributed Hierarchical Boundary =
Parasitics (Impedance)
\par }\pard\plain \widctlpar\adjustright \fs20\cgrid {This section =
defines the distributed R-C, R-L-C, and R-L-C-M parasitic boundary =
conditions for initial estimation of instantiating blocks, cells, and =
macros, and for later backannotated actual parasitics.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {The =
approach described in this section currently i
s being examined for applicability to fully accurate hierarchical net =
timing stored within the folded (instance) design hierarchy. (I =
recently found published information that this approach is in used =
within a major EDA supplier.) =20
\par The analysis and work t
odate indicates that at least of large number of nets may be accurately =
calculated from the below hierarchical two port parasitic boundary =
conditions if the timing is then captured arc-wise in a timing view =
which also have both internal and interface timi
ng arcs. An additional instance-port incremental timing offset value is =
required at the \lquote edge\rquote of the block-instance\rquote=20
s interface timing view as part of representing the information =
required for an full instantiation of a hierarchical net parasitic =
model.
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.1\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls27\ilvl2\outlin=
elevel2\adjustright \b\cgrid {
Unterminated (Open Circuit) Interface Port Parasitic (impedance) model
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {The =
Unterminated interface port parasitics model encapsulates the effects =
of the interface nets behind the port.
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.2\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls27\ilvl2\outlin=
elevel2\adjustright \b\cgrid {Terminated (Loaded) Instance (Occurrence) =
Port Parasitic (impe
dance) model=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
The terminated instance port parasitics model encapsulates the =
incremental effects of the interface nets as (potentially) loaded by =
the parasitics of the nets at the next level of the design hierarchy.
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.3\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Distributed R-C Port =
Parasitics
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.4\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Distributed R-C-L Port =
Parasitics
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.4.5\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx780\l=
s27\ilvl2\outlinelevel2\adjustright \b\cgrid {Distributed R-C-L-M Port =
Parasitics{\*\bkmkstart save
}{\*\bkmkend save}
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5\tab}}\pard\plain =
\s2\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls27\ilvl1\outlin=
elevel1\adjustright \b\cgrid {Environment Boundary Conditions
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1\tab}}\pard\plain =
\s3\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\ls27\ilvl2\outlin=
elevel2\adjustright \b\cgrid {Operating Conditions (Ambit)
\par {\listtext\pard\plain\s4 \b \hich\af0\dbch\af0\loch\f0 =
3.5.1.1\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {\cgrid0 =
set_operating_conditions
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f16\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 =
set_operating_conditions
\par }{\b\cf1\cgrid0 Syntax:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_operating_conditions ?-library =
<library_name>? <operating_condition_name>
\par }\pard \qj\sb120\widctlpar\adjustright {\b\cf1\cgrid0 =
Description:}{\b\cgrid0 }{\cgrid0 The set_operating_conditions command =
is used to specify the operating }{\cf1\cgrid0=20
conditions; process, temperature and voltage for the design from a =
given library. It is used for the mapping and optimization commands to =
select cells appropriately.
\par {\pntext\pard\plain\s44 \f3\fs20 \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright \fs20\cgrid {
\cgrid0 Each technology library contains one or more operating =
conditions.
\par {\pntext\pard\plain\s44 \f3\fs20 \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls19\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls19\adjustright {\cgrid0=20
Each condition is identified by name, which specifies the process, =
temperature and voltage as the operating condition. This information is =
used in calculating accurate cell delays from the nominal cell delays =
}{\cf1\cgrid0=20
and the k-factors (also called derating factors) using either linear =
model or non-linear model.
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\cf1\cgrid0 A list of all operating conditions in a technology library =
can be found using the report_library command.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 operating_condition_name }{\i\f17\cf1\cgrid0 =
\emdash }{\f1\fs18\cf1\cgrid0 Name of the operating condition in the
\par library
\par }{\b\cf1\cgrid0 Options:}{\b\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 -library <library_name> }{\i\f17\cf1\cgrid0 =
\emdash }{\f16\cf1\cgrid0 Name of the technology library to look for =
the operating condition name.
\par }{\b\cf1\cgrid0 Attributes:
\par Design Database:
\par Related Commands:}{\b\f1\fs18\cf1\cgrid0 }{\f1\fs18\cf1\cgrid0 =
read_alf, report_library, set_operating_parameter, =
get_operating_parameter
\par }{\b\f1\fs18\cf1\cgrid0 Examples: }{\f6\fs16\cf1\cgrid0 =
set_operating_conditions wccom}{\f16\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.2\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {On-chip or Overall =
Package Ambient Temperature

\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.3\tab}Ambient Temperature
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.4\tab}Chip Temperature
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.5\tab}Block/Cell Temperature
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.6\tab}Device Temperature
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.6.1\tab}}\pard\plain =
\s5\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls27\ilvl4\outl=
inelevel4\adjustright \b\fs22\cgrid {Device Source Field Temperature
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.6.2\tab}Device Drain Field Temperature
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b 3.6.3 =
Thermal Impedance=20
\par 3.6.3.1 Chip Over The Packaging Themal Impedance
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 3.5.1.=
7\tab}}\pard\plain =
\s4\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\l=
s27\ilvl3\outlinelevel3\adjustright \b\cgrid {Block Within The Chip =20
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.8\tab}Leaf Cell Within A Block
\par {\listtext\pard\plain\s4 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
3.5.1.9\tab}Transistor Within A Cell
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {including =
local thermal characterics (static, steady-state, transient, peak, and =
RMS) of the channel, gate, source, and drain
\par {\listtext\pard\plain\b\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
3.6.4\tab}}\pard =
\fi-720\li720\sb120\widctlpar\jclisttab\tx720\ls30\ilvl2\adjustright =
{\b Power Dissipation=20
\par }\pard \sb120\widctlpar\adjustright {\endash see above remarks on =
thermal
\par }{\b 3.6.5 Process
\par 3.6.5.1 By name within the technology library
\par 3.6.5.2 Design-Time Applicable Process Characterisitcs
\par }{including nominal, average, min, max, statistical distribution, =
and correlation with both other process characterics and environment =
conditions
\par }{\b \page=20
\par }\pard\plain \s25\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name:=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition:=20
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s25\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name:=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition:=20
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {Name:=20
\par }\pard\plain \s25\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Input Slew \endash }{\b0\i0=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: the time a signal flowing in =
through a port transistions from one digital level to another.
\par }{\b Type}{\tab =20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
\par }\pard\plain \s34\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw15\brdrcf1 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1=20
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw15\brdrcf1 \cltxlrtb \cellx12599\pard\plain =
\s18\nowidctlpar\intbl\adjustright \b\f4\fs20\cf1\cgrid {\b0\cf0 =
Name\cell Value Type\cell=20
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450 \clvertalt\cltxlrtb \cellx2250\clvertalt\cltxlrtb =
\cellx4500\clvertalt\cltxlrtb \cellx6894\clvertalt\cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{\cell \cell \cell \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450 \clvertalt\clbrdrb
\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx2250\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx4500\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx6894\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf1 \cltxlrtb =
\cellx12599\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {\cell \cell =
\cell \cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \sb120\widctlpar\adjustright {
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par=20
\par {\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 4\tab}}\pard\plain =
\s1\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw30\b=
rsp20 \jclisttab\tx432\ls27\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid {\fs20=20
\page {\*\bkmkstart _Toc422101857}Timing Hierarchical Boundary =
Conditions{\*\bkmkend _Toc422101857}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {
\par=20
\par=20
\par }}

--Boundary_(ID_eQ+DBphY6ZN6Gm8Gop3MyA)--

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