DC-WG: due 11/13/98--HDL Con paper and tutorial proposals for system, ASIC and FPGA designers

Vassilios Gerousis (gerousis@postal.sps.mot.com)
Wed, 7 Oct 1998 11:35:24 -0700 (MST)

Dear Technical Working Group Members,
HDL conference is planned for April 1999. Below is a call for papers.
Many of you have done many proposals for the OVI working groups. These should be
translated to papers and submitted to HDL conference.
In addition, I would like to see chairs & co-chair also plan meetings
during that time and also do promotion for their activities. I will ask for a
special session time to give status of the technical committees.
Also, Apply for Tutorials (Verilog-AMS, ALF and possibly Design
constraints).

Best Regards

Vassilios Gerousis
------------- Begin Forwarded Message -------------

April 6-9, 1999 ¥ Santa Clara Convention Center ¥ Santa Clara, CA

CALL FOR PAPERS

The HDL Conference is the forum for Innovative HDL Design techniques
targeting next generation and SOC designs. Now is your opportunity to
participate by submitting a paper on one of the topics listed below, or on
some unique topic of your own. Here is your chance to be recognized by a
prestigious group of designers and colleagues.

Enter the VHDL Design Contest!
The winner will be announced at the 1999 HDL Conference. See contest
details on the web at csis.ee.virginia.edu/~rhk2j/viuf/index.html.

The paper should be between 1500 and 3000 words, double spaced with 1Ó
borders. It may contain as many diagrams as needed to illustrate your key
points, but please limit the paper to a maximum of 8 pages. All accepted
paper presenters are awarded a FULL CONFERENCE REGISTRATION. All tutorial
presenters are paid based on the number of attendees.

Suggested Verilog topics are:

SYSTEM-LEVEL DESIGN
S1. HW/SW Co-Design
S2. Behavioral Coding and Synthesis
S3. Verilog and C Working Together
S4. Verilog and Verilog-A Mixed-Signal Simulation
S5. Cycle-Based Coding Techniques
S6. Formal Verification
S7. Architectural Design Trade-offs
S8. System-on-Chip Design Techniques

ASIC DESIGN
A1. Design Re-use
A2. Deep Sub-Micron Design Issues
A3. Constraint-Driven Synthesis
A4. ASIC Computer (SoC)
A5. Simulating Extremely Large ASICs
A6. Floorplanning Your RTL
A7. Advanced Techniques for Faster Simulation and Synthesis

FPGA DESIGN
F1. Mixed-Level Design (Schematic + RTL)
F2. Architecture Specific Optimization Techniques
F3. Multiple-FPGA Partitioning and Testing
F4. FPGA to ASIC Conversion
F5. Verification of Retargeted Devices
F6. State-Machine Design
F7. Timing Issues

Also: Tutorial proposals, suggestions for panels, and other ideas.

Suggested VHDL topics are:

V1. System Level Design Methods
V2. Hardware/Software Codesign
V3. Logic and State Machine Synthesis
V4. Behavioral Synthesis
V5. VHDL/Verilog Cosimulation
V6. VHDL-AMS
V7. Formal Verification
V8. Constraint Support
V9. FPGA Design
V10. Reconfigurable Computing
V11. Performance Modeling
V12. Intellectual Property Capture, Protection, & Distribution
V13. Design Reuse
V14. Design for Test
V15. Testbench Support
V16. Virtual Prototyping
V17. Advanced VHDL Applications
V18. Simulation Techniques
V19. Emulation

Also: Tutorial proposals, suggestions for panels, and other ideas.

Full Papers and Extended Tutorial Abstracts Due: NOVEMBER 13, 1998
For the latest information see: www.hdlcon.org
*Cash Prizes will be awarded for best papers, as well as the $300 full
conference registration!

For information concerning the conference contact:

Publications Department
c/o MP Associates, Inc.
5305 Spine Rd., Ste. A
Boulder, CO 80301
tel: (303) 530-4562 fax: (303) 530-4334
email: ivcviufinfo@hdlcon.org

------------- End Forwarded Message -------------