The following is inescapably 'motherhood' (for which I probably am
infamous! :-):
A constraint of any kind has, among other things, the following elements
that are used to state the constraint:
- a domain point of focus, e.g., some design goal that is desired to be met
- takes the form of the goal being stated as a <function> of available design,
environment, process and other information
+ such a function MAY include a relationship to process, temperature,
voltage, and other things. That is, the function may need to be
stated in terms of other functions and to other fundamental objects
or phenomena.
- the <function> may be stated (or evaluated) for one or more <Given
Conditions>
<ConstraintMetric> <relationship> <function> | <Given Conditions under
which
the constraint is being
measured or evaluated before
being evaluated via the
relationship.>
- The <relationship> may normally (or typically) take the form of
an equality or inequality
- the <Constraint Metric> states the desired result or goal of evaluating the
constraint's <function> per the <given conditions>.
What's the above got to do with PVT? PVT can come in two (2) ways:
- The <function> of the constraint MAY include terms or relationships of terms
which are P, V, and/or T.
+ Note that this is true even when we don't have
an easy way to state the mathematical role of P, V, and T within
the <function> definition or equation. Note that most design
timing effects needed to be constrained for, for instance, synthesis, are in
some direct or indirect way effected by the process, voltage, and/or
temperature.
- The <function> of the constraint MAY also be stated at some given values or
range of values of P, V, and T (whether or not we can put our finger on the
precise closed form relationship between PVT and the target constraint.)
So, in general:
<ConstraintMetric> <relationship> <function( {P, V, T, ...} )> for
<GivenCondition ( {P, V, T, ...} )>
So, for example, we may have a set of pin-to-pin time delays for a set
of hierarchical nets for one (or more) process 'points', supply voltages,
and overall chip or ambient temperature.
Finally, at any one point in the design process flow, we have varying
amount of information about what exactly are the process, voltage, and
temperature
values, range of values, correlation of those values, and sensitivity of
the design constraints to those design, process, and environment effects.