Thank you very much for your reply. Please see my comments below. I have checked
with people inside Synopsys to put this reply together.
> Steven Schulz wrote:
> I must tell you that I have yet to see the specifics of exactly what the SDC
> licensing consists.
Synopsys Design Constraints (SDC) licensing is similar to Liberty Licensing
Agreement. You can review sample Liberty License Agreement at the following web link
http://www.synopsys.com/partners/tapin/tapin_program.html ==> Synopsys Logic Design
Format License Agreement (MS Word Document). On the licensing question, Synopsys
has received a very positive response from EDA vendors and customers alike. The
experience has been much better than working through Standards bodies, so Synopsys
will continue with the TAP-in program.
>
> So, if I could actually preview the contents of SDC, then I would be in a better
> position to comment on a more technical foundation. I have publically stated
> my position on licensing of standards -- I do not oppose the approach if it
> represents significant IP (R&D expense) of the contributor, but it will always
> compete against any other new or existing alternatives that do not require
> licensing. .
I will send you a summary of the commands included in SDC. At present, Synopsys
have not finished the SDC User's Manual for EDA companies. Since TI is a Synopsys
customer, you can find details about the commands in the Synopsys online
documentation (SOLD).
In the past, requests for Synopsys to open their design constraints proposed putting
them in the public domain (no owner) or donating them to a standards body. Because
the design constraints change regularly, Synopsys needs a way to be able to develop
SDC in a timely manner to meet customer demands. Standards bodies or no ownership
would mean the design constraints would become stagnant. When Synopsys established
TAP-in licensing, this problem was solved. It also solved the IP question.
The SDC language contains all the constraints used to describe design intent. It
doesn't contain algorithms or synthesis specific commands. If it did contain these,
it would not be usable for non-synthesis tools such as P&R.
The SDC documentation for EDA vendors will contain syntax and descriptions of what
the constraints mean. The descriptions (you may call them semantics if you like)
will not be tool specific, but rather will have a design intent focus. For example,
a timing constraint causes different things to happen in a synthesis tool (like
add/remove gates) than in a placement tool (like assign the location of the cell).
Therefore, the description/semantics of the constraints refer to the design,
not to the tool. Another example, for instance: write_script -format design_assertios
execute command in Synopsys tools to create interchange format, this result can be
read by other EDA tools. Similarly other EDA tools can write interchange format as
inputs to Synopsys and other vendor tools.
>
> I hope this input is helpful. Let me know if you can share more details
> of the SDC licensing to aid in a more technical assessment.
>
> Steve
>
It is our hope that SDC can meet the needs of the SLDL, at least at the RTL level.
After you see the description of SDC, please let us know if this is the case.
Again, thank you for your feedback. We appreciate your perspective on this matter.
Best regards,
Ibna Faruque