US patent #: 5210700
Title: "Automatic delay adjustment for static timing analysis"
Inventor: David Tom
Issued: May 11, 1993
Abstract: Delay analysis in logic simulation is enhanced by
providing, in a simulation model of a logic circuit, a timing delay
tag on each circuit path connecting the output of a first with the
input of the second circuit element. Each circuit leg is given a delay
value and a clock phase tag providing information about how the delay
value is clocked. The clock phase tags correspond to respective phases
of a multi-phase circuit clock and relate the delay values to
particular clock phases. The phase tag also indicates whether the
signal on the data path is triggered by the rising or falling edge of
the specified clock phase. At circuit nodes, clock phase tags are
concatenated. Thus, if a clocked circuit element responds to an input
signal which is a composite of several upstream output signals, the
concatenated clock phase tags and delay values can be analyzed to
determine if a timing adjustment is required. The information further
supports the automatic adjustment of delay value, if needed.
James Swift, EDA Application Engineering Team
c/o IBM Corp, 1000 River Rd
M/S 862E Dept A6PA / Bldg 862-2, Essex Jct, VT 05452
PH 802-769-6490 or TL 446-6490 - Fax 769-7226
e-mail: jswift@us.ibm.com or James G Swift/Burlington/IBM@IBMUS