Attendees:
Mark Hahn, Cadence (Chair)
Bob Dilly, IBM
Vassilios Gerousis, Siemens
Steve Grout, Sematech
Greg Schulte, Cadence
Jim Swift, IBM
Andres Teene, LSI Logic
New action items:
Who When What
---------- ------ --------
1. Jim 2/2 Prune the list of IBM patents that might cover
the DC-WG work
2. Greg 2/2 Investigate the semantics of the BuildGates
set_port_capacitance_limit command
3. Greg, Steve 2/2 Talk about reconciling the parasitics portion
of the taxonomy with the BuildGates strawman
Open action items:
Who When What
---------- ------ --------
1. Steve, Jim, 2/2 Discuss PVT-dependent constraints and relationship
Greg to conceptual model
2. Jim 1/19 Add operating conditions to the taxonomy
-> 2/2
3. Mark, Greg 10/27 Come up with a proposal for the semantics of
-> 2/2 how source latency and jitter, common ambiguity,
common jitter, and inter-clock uncertainty relate
4. Jim 1/19 Investigate whether IBM could provide the
-> 2/2 Einstimer educational material as a reference
5. Mark 1/18 Follow up on Tau '99
-> 2/2
Closed action items:
Who When What
---------- ------ --------
1. Mark 1/18 Send DC-WG/SI2 presentation to the reflector
2. Mark 1/18 Talk with Jim Swift about operating conditions
3. Jim 1/18 Investigate IBM patents that might cover the
DC-WG work
4. Jim 1/19 Reply whether IBM will donate a strawman or
just provide review, feedback
Next Meeting:
The next meeting will be a teleconference on Tuesday, 2/2/99,
from 9-11 am PDT.
Details:
1. Review results of the vote on the Cadence/Ambit strawman
The vote was unanimously for accepting the strawman, with
one abstention (Synopsys).
2. Update from Mark's presentation to SI2 and the ASIC vendor
technical managers.
Due to a schedule mix-up, this presentation happened in afternoon
after the DC-WG teleconference, so there wasn't any update yet.
3. Update from the joint working group
Mark reviewed the status. The joint working group agreed on
a proposal from Dave Barton to define a Tcl-compatible syntax
for DCDL that will be directly embeddable in SLDL as a part of
the second phase of the SLDL work. In the first phase, there
may be a slightly different syntax for the constraints, but the
semantics will be the same.
There are some outstanding issues related to scoping and precedence
rules in declarative versus executable forms, as well as some
related issues on default constraints versus explicit constraints.
4. Review action items
Jim Swift indicated that IBM has decided to provide input on
extending the BuildGates strawman, rather than offering the
Einstimer command language as an alternate strawman. There is
some chance that IBM will provide the Einstimer educational
material as a reference in much the same way Cadence has provided
GCF as a reference, but there isn't a definitive answer to this yet.
Jim also has a list of IBM patents that might be relevant to
the DC-WG work. He is going to prune the list based on suggestions
from Mark about what areas are likely to be of concern.
5. Review Steve Grout's parasitic boundary conditions
We discussed several of the boundary conditions related to port
capacitance. In general, the document is starting to come together.
There was some debate about internal versus external capacitance,
as well as capacitance environment conditions versus capacitance
limits, and default (global) values versus specific values.
Steve and Greg planned to get together in person to work through
consistency questions between the BuildGates strawman and the
Sematech concerns.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Architect, Deep Submicron Business Unit fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com