--Boundary_(ID_C/fzpNlfRENfxf0q4MSbXg)
Content-type: text/plain; charset=iso-8859-1
This is the now complete Version 9 draft of the boundary parasitic constraints
for the DCWG synthesis constraints taxonomy. This draft adds definitions for
drive resistance and lumped and distributed impedance RC, RCL, and RCLM port
parasitics.
Many thanks to Greg Schulte for his recent help in both reviewing the approach
taken and identifying exactly what terms are needed for the current DCWG work.
Regards,
--Steve Grout
> -----Original Message-----
> From: Steve.Grout@SEMATECH.Org [mailto:Steve.Grout@SEMATECH.Org]
> Sent: Tuesday, February 16, 1999 11:15 AM
> To: dcwg@eda.org
> Subject: DC-WG: RE: Version 8 of the DCWG boundary parasitic
> constraints
>
>
> The attached is the now-almost complete Version 8 draft of
> the boundary
> parasitic constraints for the DCWG synthesis constraint.
> - Not yet completely drafted are definitions for drive cell,
> drive resistance and drive capacitance - These will be defined
> and completed just after today's telcon, working from the
> definitions within the AMBIT strawman.
>
> This edition reflects the recent joint discussion with Greg
> Schulte on the underlying computational and usage model for
> constraints and related assertions, especially as used within
> the AMBIT synthesis constraint strawman.
>
> I will add the remaining 3 term definitions and submit it to the
> reflector as version 9 later today.
>
>
> --Steve Grout
>
> Attachment: Parasitics08sg.rtf
>
>
--Boundary_(ID_C/fzpNlfRENfxf0q4MSbXg)
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}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385942 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340032000000}}}{\fldrslt {\lang1024 =
9}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.3.1\tab Output Port Wire Load (Ambit) \endash =
general\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385943 \\h =
}}{\fldrslt {\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.4\tab Global Capacitance Limit -yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385944 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340034000000}}}{\fldrslt {\lang1024 =
10}}}{\lang1024=20
\par 1.4.1.1.5\tab Input Port Lumped RC Parasitic Model \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385945 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900340035000000}}}{\fldrslt {\lang1024 =
11}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.5.1\tab Output Port Internal Lumped RC parasitic =
model \endash general - new\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385946 \\h }}{\fldrslt {
\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.6\tab Output Port Distributed Hierarchical Boundary =
Parasitics (Impedance) \endash general - new\tab }{\field{\*\fldinst =
{\lang1024=20
PAGEREF _Toc443385947 \\h }}{\fldrslt {\b\lang1024 Error! Bookmark not =
defined.}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.6.1\tab Unterminated (Open Circuit) Interface Output =
Port Parasitic (impedance) model \endash general -new\tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385948 \\h }}{\fldrslt {\b\lang1024 Error! Bookmark not =
defined.}}}{\lang1024=20
\par 1.4.1.1.6.2\tab Terminated (Loaded) Instance (Occurrence) Output =
Port Parasitic (impedance) model - general - new\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385949 \\h }}{\fldrslt =
{\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par 1.4.1.1.6.3\tab Distributed R-C Output Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385950 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350030000000}}}{\fldrslt {\lang1024 =
11}}}{\lang1024=20
\par 1.4.1.1.6.4\tab Distributed R-C-L Output Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385951 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350031000000}}}{\fldrslt {\lang1024 =
12}}}{\lang1024=20
\par 1.4.1.1.6.5\tab Distributed R-C-L-M Output Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385952 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350032000000}}}{\fldrslt {\lang1024 =
13}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.7\tab Input Port Distributed Hierarchical Boundary =
Parasitics (Impedance) \endash general - new\tab }{\field{\*\fldinst =
{\lang1024=20
PAGEREF _Toc443385953 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350033000000}}}{\fldrslt {\lang1024 =
14}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.1.7.1\tab Unterminated (Open Circuit) Interface Input =
Port Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385954 \\h }{
\lang1024 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000=
000e0000005f0054006f0063003400340033003300380035003900350034000000}}}{\f=
ldrslt {\lang1024 14}}}{\lang1024=20
\par 1.4.1.1.7.2\tab Terminated (Loaded) Instance (Occurrence) Input =
Port Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385955 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350035000000}}}{\fldrslt {\lang1024 =
15}}}{\lang1024=20
\par 1.4.1.1.7.3\tab Distributed R-C Input Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385956 =
\\h }}{\fldrslt {\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par 1.4.1.1.7.4\tab Distributed R-C-L Input Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385957 =
\\h }}{\fldrslt {\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par 1.4.1.1.7.5\tab Distributed R-C-L-M Input Port Parasitics \endash =
general - new\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385958 =
\\h }}{\fldrslt {\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s37\li200\widctlpar\tx1200\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2\tab Input Port Specific Parasitic Boundary =
Conditions\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385959 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900350039000000}}}{\fldrslt {\lang1024 =
15}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.2\tab Input Port External Environment Constraints\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385960 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360030000000}}}{\fldrslt {\lang1024 =
16}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.2.1\tab Number External Sources (Ambit \endash =
num_external_sources) - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385961 \\h }{\lang1024=20
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360031000000}}}{\fldrslt {\lang1024 =
16}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.1.2.1.1}{\lang1024 \tab }{\lang1024\cgrid0 =
Reference only \endash set_num_external_sources(Ambit)}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385962 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360032000000}}}{\fldrslt {\lang1024 =
16}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.3\tab Input Port Internal Implementation =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385963 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360033000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.1.3.1\tab Drive Strength : - yes\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385964 \\h }}{\fldrslt {\b\lang1024 Error! =
Bookmark not defined.}}}{
\lang1024=20
\par }\pard\plain =
\s37\li200\widctlpar\tx1200\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2\tab Output Port Parasitic Boundary Conditions\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385965 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360035000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1\tab Output port External Environment Constraints\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385966 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360036000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1.1\tab Fanout Load (Ambit) - yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385967 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900360037000000}}}{\fldrslt {\lang1024 =
17}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1.1.1\tab Fanout \endash same as fanout load\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385968 \\h }}{\fldrslt =
{\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par 1.4.2.1.1.2\tab Fanout Drive \endash same as fanout load\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385969 \\h }}{\fldrslt =
{\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1.2\tab Fanout Load Limit (Ambit) - yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385970 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370030000000}}}{\fldrslt {\lang1024 =
18}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.2.1.2.1}{\lang1024 \tab }{\lang1024\cgrid0 =
Reference - set_fanout_load_limit (Ambit)}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024=20
PAGEREF _Toc443385971 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370031000000}}}{\fldrslt {\lang1024 =
18}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.1.3\tab Number External Sinks - ??? TBD\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385972 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370032000000}}}{\fldrslt {\lang1024 =
19}}}{\lang1024=20
\par 1.4.2.1.4\tab Output Port External Fanout <redundant?>\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385973 \\h }}{\fldrslt =
{\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2\tab Output Port Internal Implementation =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385974 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370034000000}}}{\fldrslt {\lang1024 =
21}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2.1\tab Cell (Block) Drive (Ambit) \endash Drive cell =
-yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385975 \\h =
}}{\fldrslt {\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par 1.4.2.2.2\tab Effective Drive Internal Capacitance \endash Drive =
Capacitance - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385976 \\h }}{\fldrslt {\b\lang1024 Error! Bookmark not =
defined.}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2.2.1\tab Output Port Drive Capability =3D Drive =
Capacitance - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385977 \\h }}{\fldrslt {\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.2.3\tab Drive resistance (Ambit) yes\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385978 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370038000000}}}{\fldrslt {\lang1024 =
21}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024\cgrid0 1.4.2.2.3.1}{\lang1024 \tab }{\lang1024\cgrid0 =
set_drive_resistance}{\lang1024 \tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc443385979 \\h }{\lang1024=20
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340033003300380035003900370039000000}}}{\fldrslt {\lang1024 =
22}}}{\lang1024=20
\par 1.4.2.2.3.2\tab Effective Drive Internal Resistance \endash Drive =
Resistance - yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385980 \\h }}{\fldrslt {\b\lang1024 Error! Bookmark not =
defined.}}}{\lang1024=20
\par }\pard\plain =
\s38\li400\widctlpar\tx1400\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.3\tab Items which are NOT Boundary Parasitics data or =
constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385981 =
\\h }}{\fldrslt {\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain =
\s39\li600\widctlpar\tx1705\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.3.1\tab Wire Load Model (Ambit) \endash general - =
yes\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc443385982 \\h =
}}{\fldrslt {\b\lang1024=20
Error! Bookmark not defined.}}}{\lang1024=20
\par 1.4.2.3.2\tab Custom Wire Load Mode (Ambit) \endash yes \endash =
not equivalent\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc443385983 \\h }}{\fldrslt {\b\lang1024 Error! Bookmark not =
defined.}}}{\lang1024=20
\par }\pard\plain =
\s40\li800\widctlpar\tx2058\tqr\tldot\tx8630\adjustright \fs20\cgrid =
{\lang1024 1.4.2.3.2.1\tab Output Port Equivalent Custom Wire Load =
\endash general \endash not equivalent\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc443385984 \\h }
}{\fldrslt {\b\lang1024 Error! Bookmark not defined.}}}{\lang1024=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
}}\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\kerning28 =
\sect }\sectd =
\marglsxn1440\margrsxn2160\margtsxn1613\margbsxn1685\psz1\sbkcol\linex0\=
colsx0\titlepg\sectdefaultcl=20
{\*\bkmkstart clock}{\*\bkmkstart parasitics}{\*\bkmkstart =
_Toc443385932}{\*\bkmkstart _Toc422101856}{\*\bkmkend clock}{\*\bkmkend =
parasitics}{\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 1\tab}\pard\plain=20
\s1\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw30\b=
rsp20 \jclisttab\tx432\ls53\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid {\fs20 Design Constraints \endash Especially =
Timing Constraints Driving Synthesis
{\*\bkmkend _Toc443385932} {\*\bkmkend _Toc422101856}
\par {\*\bkmkstart _Toc443385933}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.1\tab}}\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls53\ilvl1\out=
linelevel1\adjustright \b\cgrid {(See ParasaticsDiscussion04sg)
{\*\bkmkend _Toc443385933}
\par {\*\bkmkstart _Toc443385934}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.2\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc443385934}
\par {\*\bkmkstart _Toc443385935}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.3\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc443385935}
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4\tab}\page {\*\bkmkstart _Toc443385936}Parasitic Boundary =
Conditions{\*\bkmkend _Toc443385936}=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {This =
section defines constraint terms for parasitic boundary conditions and =
may appl. =20
\par Note that, when available and where applicable, the related term =
definition from the Ambit constraint strawman is also included for =
reference.
\par {\*\bkmkstart mark}{\*\bkmkstart _Toc443385937}{\*\bkmkstart =
_Toc432826548}{\*\bkmkstart _Toc434042497}{\*\bkmkstart =
_Toc434061598}{\*\bkmkend mark}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1\tab}}\pard\plain=20
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls57\ilvl2\outlinelevel2\adjustright \b\cgrid {Port General Parasitic =
Boundary Conditions{\*\bkmkend _Toc443385937}
\par }\pard\plain \qj\widctlpar\adjustright \fs20\cgrid {The following =
parasitic constraint definitions apply to both input and output ports =
or port types.}{\cs46\super \chftn {\footnote \pard\plain =
\s45\qj\sb120\widctlpar\adjustright \fs20\cgrid {}}}{
\par {\*\bkmkstart _Toc443385938}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Port Capacitance
{\*\bkmkend _Toc443385938}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance }{\fs16=20
\par }\pard\plain =
\s28\li288\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0=20
Specifies the sum of the capacitance at a port of the cell, block or =
design based on the contribution of individual port capacitances from =
other input and output ports connected by nets to a target port.
\par }\pard =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
{\cgrid0=20
The total capacitance at any port is the sum of the individual =
contributions of external and internal port capacitances to which the =
port is connected. A port capacitance may be defined within either a =
design hierarchy or within a flatten
ed occurrence design. =20
\par Note that the port capacitance does not include any capacitance =
contribution of the port itself. This capacitance also does not =
include capacitance contribution of the net lying behind the port =
inside the cell.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b DCWG Issue:}{ Discussions with Ambit I believe led =
to the conclusion that this term would necessarily include any possible =
\lquote port self capacitance
\rquote .
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\cgrid0 For an input port, the Port Capacitance refers =
to the individual capacitances contributed by all of the other ports =
that drive to
the port via a hierarchical net, and the capacitance of the other =
loads on the hierarchical net.=20
\par For output ports, the port capacitance refers to the capacitance =
of all the external sinks, and/or external drivers, for the case of a =
multiply-driven net, t
hat are connected to the hierarchical net. This capacitance includes =
capacitance contributions of other input ports of any other external =
drivers connected to the hierarchical net.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b DCWG Issue:}{ The name of this assertion is too =
generic as the name is appro
priate for the individual port capacitance contributions that are =
summed within it. It is proposed to be renamed \lquote }{\i total port =
capacitance}{\rquote or \lquote }{\i aggregate port =
capacitance}{\rquote .
\par }{\b Type}{\tab Parasitic Boundary Condition Assertion
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Ports of a cell definition, cell =
instance, or flattened cell=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{
Its own capacitance and the capacitances of the other ports connected =
to the same hierarchical net. Also depends on Port Capacitance Limit.
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdr=
w30\brdrcf1 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell List of Identifier\cell Only one port on a =
hierarchical net needs to be identified.\cell=20
Identifies one or more ports on the target cell or cell instance that =
will have the aggregate capacitance value.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
Target cell or cell instance\cell Identifier\cell Cell must exist in =
the target design hierarchy\cell Name of the cell (if the top cell) or =
cell instance\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\trowd \trgaph108\trleft450\trbrdrt
\brdrs\brdrw30\brdrcf1 \trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10170\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Capacitance =
value\cell Farad Floating value\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.
\par The unit of capacitance will be the same as that used in the =
library or sourcing database.\cell Sum of the individual capacitance =
contributions of the ports of the hierarchical network connected to the =
target port\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row {\*\bkmkstart =
_Toc443385939}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar
\jclisttab\tx1152\ls53\ilvl5\outlinelevel5\adjustright \i\fs22\cgrid =
{\cgrid0 Reference only: set_port_capacitance }{\fs20 =
(Ambit){\*\bkmkend _Toc443385939}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f20\cf1\cgrid0 Command}{\f20\cf1\cgrid0 : }{\f6\fs16\cf1\cgrid0 =
set_port_capacitance
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 =
Syntax:}{\b\f1\fs18\cgrid0 :}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance <capacitance> <port_list>
\par }{\b\cgrid0 Description: }{\cgrid0 The }{\f6\fs16\cgrid0 =
set_port_capacitance }{\cgrid0 command specifies the capacitance =
external to the design based on input and output loading from other =
ports and nets connected to the ports of the current module.
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {\cgrid0 =
The capacitance at any port is the sum of the external port =
capacitances the port is connected to. For an input port the port =
capacitance refers to the capacitance of all the ports of the driver =
that are connected to the net and the capacitance o
f the other loads on the net. For output ports, the port capacitance =
refers to the capacitance of all the external sinks, or external =
drivers, for the case of multiply-driven net, that are connected to the =
net as well as the capacitance of the input port=20
of any other external drivers.
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Arguments: =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f21\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par port_list }{\i\f21\cgrid0 \emdash }{\f1\fs18\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
None
\par }{\b\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb240\widctlpar\adjustright {\b\cgrid0 Design Database: =
}{\cgrid0 None
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_current_module, set_port_capacitance_limit
\par }{\b\cgrid0 Examples: }{\cgrid0 This command sets a 3.2 =
capacitance on all output ports of the current module whose names match =
dbus at the start The unit of capacitance will be the same as the unit =
of capacitance used in the library.
\par }\pard \fi720\sb120\widctlpar\adjustright {\f2\cgrid0 =
set_port_capacitance 3.2 [find -port \endash output }{\f2\cf1\cgrid0 =
bus*]
\par {\*\bkmkstart _Toc443385940}{\listtext\pard\plain\s5 \b\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\cgrid0 Port Capacit
ance Limit {\*\bkmkend _Toc443385940}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{ }{\cgrid0=20
Specifies the maximum value of the sum of capacitance external to the =
target port based on the sum of all the individual capacitance =
contributions of all input and output ports that are hierarc
hically connected to the target port. This constraint may be used to =
override global port capacitance constraints.
\par This constraint may be specified on a cell interface =
(input}{\f20\cgrid0 or output) port of a design hierarchy, including =
}{\cgrid0 on a port of a top }{\f20\cgrid0 level cell.=20
This sets the constraint that the total capacitance (i.e., net or wire =
capacitance and port capacitance) of hierarchical nets attached to the =
ports in the port list do not exceed the specified maximum value of =
capacitance.=20
\par This constraint may be used to override the default capacitance =
limit constraint that may be separately set by the }{\f6\cgrid0 =
Global_Port_Capacitance_Limit constraint}{\f1\cgrid0 .}{\f1\fs18\cgrid0 =
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard =
\s30\li288\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright {\b =
Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Ports of a cell definition, cell =
instance, or flattened cell occurrence
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for =
capacitance loading of an input or output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid { =
=
=20
=
=
=
=20
Target Port name or list\cell List of Identifier\cell The target =
port(s) must exist within target cell\cell Identifies all the ports =
that are to have the port capacitance limit value\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row=20
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell or cell instance\cell Identifier\cell Cell must exist in =
the target design hierarchy\cell Name of the cell (if the top cell) or =
cell instance\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Capacitance =
limit value\cell Farad as Float\cell Zero or greater value in farads. =
ISO/IEEE postfix multiplier may be used, e.g., uF, nF, pF, etc. \cell=20
Maximum value of capacitance of the ports and net external to the =
target ports\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid =
{\row }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385941}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
Reference only: set_port_capacitance_limit }{(Ambit)}{\cgrid0 =
{\*\bkmkend _Toc443385941}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
{\b\f20\cgrid0 Command:}{\f20\cgrid0 }{\cgrid0 =
set_port_capacitance_limit
\par }{\b\fs18\cgrid0 Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance_limit <capacitance> <port_list>
\par }{\b\fs18\cgrid0 Description:}{\cgrid0 The }{\fs16\cgrid0 =
set_port_capacitance_limit }{\cgrid0 command specifies the limit on the =
}{\fs18\cgrid0 capacitance}{\cgrid0 (maximum value) external to the =
design based on input }{\fs18\cf1\cgrid0=20
and output loading from other ports and nets connected to the ports of =
the current module. }{\cf1\cgrid0 It is used to override design rule =
constraints set by the global attribute
\par }{\b\fs18\cgrid0 set_capacitance_limit:}{\cgrid0 These =
constraints can be specified on top }{\f20\cf1\cgrid0=20
level input and output ports. It sets the constraint that the total =
capacitances (i.e., wire capacitance and pin capacitance) of nets =
attached to the ports in the port list do not exceed the specified =
capacitance li
mit. This command overrides the default limit set by the =
}{\f6\fs16\cf1\cgrid0 set_global_capacitance_limit }{\f20\cf1\cgrid0 =
command}{\f1\fs18\cf1\cgrid0 .
\par }{\b\fs18\cgrid0 Arguments:}{\cgrid0 =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f21\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f21\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\fs18\cgrid0 =
Options:}{\cgrid0 None
\par }{\b\fs18\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb120\nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_fanout_load_limit, }{\f1\fs18\cf1\cgrid0=20
set_slew_limit, set_port_capacitance, set_num_external_sources, =
set_num_external_sinks, do_derive_context, do_time_budget, set_global =
capacitance_limit
\par }{\b\cgrid0 Examples:}{\f1\cgrid0 }{\cgrid0 =
set_port_capacitance_limit 5.0 [find -port dbus*]
\par=20
\par {\*\bkmkstart _Toc443385942}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Port Wire Load Model
{\*\bkmkend _Toc443385942}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Wire Load
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{ }{\cgrid0=20
Specifies the wire load model for either an input or output port of a =
hierarchical design, including the top level cell or block. The net =
connected to the port is associated with the specified port wire load =
model and=20
used for wire capacitance and resistance estimation. If a net is =
connected to more than one port with a port_wire_load_model assertion, =
then the worst wire load model is computed and used for the net. The =
library name indicates the location of the specifi
ed wire load model information. If the library is not specified, then =
the port wire load model information is used that is defined in the =
target or default technology.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition, cell =
instance port, or flattened cell occurrence port
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Technology definition of wire load =
model to be associated with a target port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell \cell Identifies the input port on =
the target cell or cell instance \cell=20
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell Cell must exist in the target design =
hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Wire load =
model\cell Identifier\cell \cell=20
Identifies the wire load model information\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 \trbrdrb\brdrs\brdrw1=
0 \trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb
\brdrs\brdrw10 \cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb=20
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Library\cell Identifier\cell Optional\cell Identifies the =
library that contains the wire load model information.\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\listtext\pard\plain\s6 \i\fs20 \hich\af0\dbch\af0\loch\f0 =
1.4.1.1.3.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\fs20\cgrid0=20
For Reference Only: set_port_wire_load (Ambit) \endash =20
\par }\pard\plain =
\s25\qj\fi-720\li720\sb240\keepn\widctlpar\adjustright \b\i\fs20\cgrid =
{Name: }{\cgrid0 set_port_wire_load}{
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {\b =
Semantic definition:}{ }{\cgrid0 The set_port_wire_load command =
specifies the wire load for either an input or out
put top level port of a design. The net connected to the port is =
associated with the specified wire load model, which is used for wire =
cap and resistance estimation. If a net is connected to more than one =
port with a set_port_wire_load assertion, then the
worst wire load model is computed and used for the net. The library =
name indicates the location of the specified wire load model. If the =
library is not specified, then the wire load is located from the target =
technology (the default location).
\par }{\b\cgrid0 Syntax:}{\cgrid0 set_port_wire_load ?-library =
<library_name>? <wire_load> <port_list>
\par }{
\par {\*\bkmkstart _Toc443385944}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Global Capacitance Limit{\*\bkmkend _Toc443385944}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Global Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{ }{\cgrid0 Specifies the =
default maximum value of aggregate port capacitance defined to exist =
for all or a list of target ports. =20
\par This constraint may be specified on a cell interface port of a =
design hierarchy, including on a top level port. This defines the =
constraint of the default maximum aggregate port capacitance of =
hierarchical design network that may be associated with
a list of target ports. This constraint may be overridden for one or =
more ports by defining a port capacitance limit constraint.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {DCWG Issue: This constraint may be also overridden by =
defining an aggregate }{\cgrid0 port capacitance assertion for one or =
more target ports.}{
\par }{\cgrid0 DCWG Issue: Global values need to be resolved as part of =
the defaults.}{
\par }{\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for default =
maximum capacitance loading of a port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Default =
External Capacitance value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Default maximum value of capacitance =
of the ports and net external to the target ports\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\widctlpar\adjustright {
\par \page=20
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.1.1.5\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Non-Lumped Capacitance Parasitic Boundary Constrants:
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {\b DCWG =
Issue:}{ The parasitic boundary assertions and constraints defined in =
this draft are targeted for use in constrainin
g and/or estimating technologies which are amenable to lumped =
capacitance estimation techniques. It is believed that technologies =
for smaller feature sizes (e.g., 250nm and below) will probably need to =
be based on use of lumped and/or distribution RC, RL
C, RLCM, (and possibly AWE-based polynomial) approximations for planned =
and actual nets.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls45\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls45\adjustright \fs20\cgrid {
The following several terms are included in this draft in order to open =
discussions on how to approach constraints and assertions for these =
other net representation models.
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc443385945}{\listtext\pard\plain\s6 =
\b\i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 1.4.1.1.5.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b=20
Lumped RC Port Parasitic Model{\*\bkmkend _Toc443385945}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Lumped RC Parasitic Model
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
Semantic definition: Specifies the distributed parasitic effects of a =
net or net-segment at a given input port as a single lumped-value of =
capacitance and resistance. =20
\par Lumped RC parasitic models may be specified from which to =
calculate corresponding nominal, best-case, and/or worst-case net or =
net-segment delay, slew, and other related timing characteristics.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The RC parasitic net impedance and =
timing estimation model to be associated with one or more ports
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
Lumped parasitic series R value\cell Float in ohms\cell Equal to or =
greater than zero ohms\cell The R component of the lumped RC parasitic =
model\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt
\brdrs\brdrw30\brdrcf1 \trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Lumped =
parasitic parallel C value\cell Float in farads\cell=20
Equal to or greater that zero farads\cell The C component of the lumped =
RC parasitic model\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard \sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc443385950}{\listtext\pard\plain\s6 =
\b\i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 1.4.1.1.5.2\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b=20
Distributed R-C Port Parasitic{\*\bkmkend _Toc443385950} Model
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Distributed R-C Port Parasitic Model
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies the distributed =
parasitic effects of a net or net-segment at a given input port as a =
distributed RC parasitic model.=20
\par Port impedance RC models of distributed parasitic may be specified =
from which to calculate corresponding nominal, best-case, and/or =
worst-case net or net-segment delay, slew, and other related timing =
characteristics.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The RC parasitic net impedance and =
timing estimation model to be associated with one or more ports
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the input
port on the target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
One of more sections of a distributed parasitic series R value\cell =
Float in ohms\cell Equal to or greater than zero ohms\cell The R =
component of a multi-section distributed RC parasitic model\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {
\row }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb=20
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
One or more sections of a distributed parasitic parallel C value\cell =
Float in farads\cell Equal to or greater that zero farads\cell The C =
component of a multi-section distributed RC parasitic model\cell =
}\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385951}{\listtext\pard\plain\s6 =
\b\i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 1.4.1.1.5.3\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b=20
Distributed R-C-L Port Parasitic{\*\bkmkend _Toc443385951} Model
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Distributed R-C-L Port Parasitic Model=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies the distributed =
parasitic effects of a net or net-segment at a given input port as a =
multi-section distributed R-C-L m
odel of capacitance, inductance, and resistance. =20
\par Distributed R-C-L port parasitic models may be specified from =
which to calculate corresponding nominal, best-case, and/or worst-case =
net or net-segment delay, slew, and other related timing =
characteristics.
\par=20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The RCL parasitic net impedance =
and timing estimation model to be associated with one or more ports
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
One of more sections of a distributed parasitic series R value\cell =
Float in ohms\cell Equal to or greater than zero ohms\cell The R =
component of a multi-section distributed RC parasitic model\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {One or more sections of a distributed series L value\cell =
Float in henrys\cell Equal to or greater that zero henrys\cell=20
The L component of a multi-section distributed RCL parasitic model\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb
\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {One or more =
sections of a distributed parasitic parallel C value\cell Float in =
farads\cell Equal to or greater that zero farads\cell The C component=20
of a multi-section distributed RCL parasitic model\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\sb120\widctlpar\adjustright {{\*\bkmkstart _Toc443385952}
\par {\listtext\pard\plain\s6 \b\i\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.5.4\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b Distributed R-C-L-M Port =
Parasitics
{\*\bkmkend _Toc443385952}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: =20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
Semantic definition: Specifies the distributed parasitic effects of a =
net or net-segment at a given input port as a multi-section distributed =
R-C-L-M model of capacitance, inductance, mutual inductance, and =
resistance. =20
\par Distributed R-C-L-M port parasitic models may be specified from =
which to calculate corresponding nominal, best-case, and/or worst-case =
net or net-segment delay, slew, and other related timing =
characteristics.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The RCLM parasitic net impedance =
and timing estimation model to be associated with one or more ports
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab=20
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
One of more sections of a distributed parasitic series R value\cell =
Float in ohms\cell Equal to or greater than zero ohms\cell The R =
component of a multi-section distributed RC parasitic model\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {One or more sections of a distributed series L value\cell =
Float in henrys\cell Equal to or greater that zero henrys\cell=20
The L component of a multi-section distributed RCL parasitic model\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {
One or more sections of a distributed parasitic parallel C value \cell =
Float in farads\cell Equal to or greater that zero farads\cell The C =
component of a multi-section distributed RCLM parasitic model\cell =
}\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {One or more =
sections of a distributed parasitic series L value that is coupled to =
some other net or port\cell Float in henrys\cell Equal to or greater =
that zero henry
\cell The L component of a multi-section distributed RCLM parasitic =
model\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \clvertalt
\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {One or more =
sections of a distributed parasitic parallel M value that is coupled =
to some other net or port\cell Float in henrys\cell=20
Equal to or greater that zero henrys\cell The M component of a =
multi-section distributed RCLM parasitic model\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385953}{\listtext\pard\plain\s6 =
\b\i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 1.4.1.1.5.5\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b=20
Port Distributed Hierarchical Boundary Parasitics =
(Impedance){\*\bkmkend _Toc443385953}
\par }\pard\plain \widctlpar\adjustright \fs20\cgrid {This section =
defines the distributed R-C, R-L-C, and R-L-C-M parasitic boundary =
conditions for initial estimation of instantiating blocks, cells, and =
macros, and for later backannotated actual parasitics.
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {
The approach described in this section currently is being examined for =
applicability to fully accurate hierarchical net timing stored within =
the folded (instance) design hierarchy per the approach published in =
ISPD98 and other publishe
d information that this approach is in used within a major EDA =
supplier.
\par The analysis work and results todate indicates that at least of =
large number of nets may be accurately calculated from the below =
hierarchical two port parasitic boundary conditions if
the timing is then captured arc-wise in a timing view which also have =
both internal and interface timing arcs. An additional instance-port =
incremental timing offset value is required at the \lquote edge\rquote =
of the block-instance\rquote=20
s interface timing view as part of representing the information =
required for an full instantiation of a hierarchical net parasitic =
model.
\par {\*\bkmkstart _Toc443385954}{\listtext\pard\plain\s7 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.5.5.1\tab}}\pard\plain =
\s7\qj\fi-1296\li1296\sb240\sa60\widctlpar\jclisttab\tx1296\ls53\ilvl6\o=
utlinelevel6\adjustright \f1\fs20\cgrid {\b\f0=20
Unterminated (Open Circuit) Interface Port Parasitic (impedance) =
model{\*\bkmkend _Toc443385954}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Unterminated (Open Circuit) Interface Port =
Parasitic (impedance) Model
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {Semantic =
definition: Specifies an interface input port parasitics model under =
open-circuit conditions. =20
\par This model encapsulates the effects of the loaded and driven =
interface net behind the input port. The open-circuit input port model =
can be used when the cell is instantiated to develop the timing of a =
hierarchical involving the target input port.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Port of a cell definition =
interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The electrical parasitic model of =
net and other connected ports behind the target input port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab Extraction or ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell Ce
ll must exist in the target design hierarchy\cell name of the cell (if =
the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Input port Parasitic model under external open circuit =
conditions\cell=20
A group of float values representing the unterminated impedance\cell =
Greater than zero in magnitude\cell Parasitic impedance of the unloaded =
net laying behind the target input port.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard=20
\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385955}
\par {\listtext\pard\plain\s7 \b\fs20\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.1.1.5.5.2\tab}}\pard\plain =
\s7\qj\fi-1296\li1296\sb240\sa60\widctlpar\jclisttab\tx1296\ls53\ilvl6\o=
utlinelevel6\adjustright \f1\fs20\cgrid {\b\f0=20
Terminated (Loaded) Instance (Occurrence) Port Parasitic (impedance) =
Model{\*\bkmkend _Toc443385955}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Terminated (Loaded) Instance (Occurrence) Port =
Parasitic (impedance) Model
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies a parasitics model of a =
loaded input port.
\par This input port parasitics model encapsulates the incremental =
effects of an hierarchical net loaded by both the interface loaded net =
and the parasitics of the loaded net at the next level of the design =
hierarchy.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Port of a cell instance =
interface as part of a hierarchical net
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{the contributions of the loaded =
interface net behind the target port and the loaded internal net of the =
next level=20
of the design hierarchy when the target cell is instantiated as an =
occurrence.
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC or extraction
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the input port on the target
cell or cell instance \cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell Cell must exist in the target design =
hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Input port =
Parasitic model under external loaded circuit conditions\cell A group =
of float values representing the terminated impedance\cell=20
Greater than zero in magnitude\cell Parasitic impedance of the loaded =
net laying behind the target input port.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385959}
\par {\listtext\pard\plain\s3 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.2\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls57\ilvl2\outlinelevel2\adjustright \b\cgrid {Input Port Specific =
Parasitic Boundary Conditions
{\*\bkmkend _Toc443385959}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {The =
following constraint definitions are specific to input ports.
\par {\*\bkmkstart _Toc443385960}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls53\ilvl3\outlinelevel3\adjustright \b\cgrid {Input Po
rt External Environment Constraints{\*\bkmkend _Toc443385960}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart InputPortExternal}{\*\bkmkend InputPortExternal}
The following are descriptions and constraints found at the input ports =
of the external implementation or instance of block when it is used =
within a design hierarchy. That is, these constraints describe or =
prescribe tho
se properties of the environment surrounding the use of an input port =
of an instance of a block. These constraints are part of the =
characteristics of what may or should happen at or near the input port =
of an instance of a block when later signals propagat
e to the input port via the surrounding interconnect at the next level =
of the design hierarchy.
\par=20
\par {\*\bkmkstart _Toc443385961}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Number External Sources (Ambit \endash num_external_sources) - =
yes{\*\bkmkend _Toc443385961}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Number External Sources
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Semantic definition:}{ Specifies the number of =
actual external ports=20
that are or may be connected to the target port of a cell or cell =
instance and are driving it. }{\cgrid0 This number is factored into the =
wire capacitance and wire resistance estimation done for the net =
connected to the target port.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Hierarchical connectivity fan-in
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Namev\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the input port on the tar
get cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell Cell must exist in the target design =
hierarchy\cell=20
name of the cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10=20
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Number =
external ports\cell Float\cell \cell Number of actual or potential =
ports external to the target port\cell }\pard\plain =
\widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385962}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0 Reference only=20
\endash set_num_external_sources(Ambit){\*\bkmkend _Toc443385962}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f20\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 =
set_num_external_sources
\par }{\b\cf1\cgrid0 Syntax: }{\cf1\cgrid0 set_num_external_sources =
<num_sources> <port_list>
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 Description: =
}{\cf1\cgrid0 The set_num_external_sources command can be specified on =
top level input and output ports. This command sets t
he constraint that the number of external sources specified by the =
command are connected to the ports in the port list. This number is =
factored into the wire capacitance and wire resistance estimation done =
for the port nets using the wire load models.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f1\fs18\cf1\cgrid0 num_sources \emdash Number of external sources
\par }\pard \sb120\nowidctlpar\adjustright {\f1\fs18\cf1\cgrid0 =
port_list \emdash List of ports
\par }\pard\plain \s18\nowidctlpar\adjustright \b\f4\fs20\cf1\cgrid =
{\f0\cgrid0 Options:
\par Attributes:
\par Design Database:
\par Related Commands:
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\b\cf1\cgrid0 =
Examples:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs18\cf1\cgrid0 =
set_num_external_sinks
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs18\cf1\cgrid0 =
set_port_capacitance
\par do_derive_context
\par do_time_budget}{\f20\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385963}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls53\ilvl3\outlinelevel3\adjustright \b\cgrid {
Input Port Internal Implementation Constraints{\*\bkmkend =
_Toc443385963}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart InputPortInternal}{\*\bkmkend InputPortInternal}
The following are definitions and constraints found at the input ports =
of the internal definition or implementation of a block that will later =
be reused as a block instance in a design hierarchy (and as an =
occurrence in the unfolded design). That
is, these definitions and constraints are those properties of an input =
port and possibly its associated interconnect found within a design =
definition of a design hierarchy. These constraints are part of the =
characteristics of what may or should happen=20
at or near the input port when signals flow in through the input port =
to the rest of the block definition via the associated nearby =
interconnect.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls45\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls45\adjustright \fs20\cgrid {
None found
\par {\*\bkmkstart _Toc443385965}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls53\ilvl2\outlinelevel2\adjustright \b\cgrid {
Output Port Parasitic Boundary Conditions{\*\bkmkend _Toc443385965}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc443385966}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1\tab}}\pard\plain \s4\qj\fi-864\li864\=
sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx864\ls53\ilvl3\outline=
level3\adjustright \b\cgrid {
Output port External Environment Constraints{\*\bkmkend _Toc443385966}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart OutputPortExternal}{\*\bkmkend OutputPortExternal}The =
followin
g are descriptions and constraints found at the output ports in an =
external implementation of a cell or block or for an instance of a =
block definition when the block is used within a design hierarchy. =
That is, these constraints describe or prescribe thos
e
properties of the environment surrounding the use of an output port of =
an instance of a block. These constraints are part of the =
characteristics of what may or should happen at or near the output port =
of an instance of a block when, later, signals propa
gate out through the output port to the interconnect of the next higher =
level part of the design hierarchy.
\par=20
\par {\*\bkmkstart _Toc443385967}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Fanout Load (Ambit) - yes{\*\bkmkend _Toc443385967}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Fanout Load
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {Semantic =
definition:}{\f6\fs16\cgrid0 }{\cgrid0 Specifies the expected or =
budgeted fanout load on the ports of a cell when the cel
l is instantiated. While port capacitance affects timing analysis, =
fanout loads are used during planning the loading of a cell, and later =
to enforce the design rule checks of the application or use a cell.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition =
interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{The number of load or input ports =
that can be connected by a net to an output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Fanout value\cell Integer\cell >=3D 0\cell Number of ports =
that the target port may drive\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\qj\sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s6 \b\i\fs22 \hich\af0\dbch\af0\loch\f0 =
1.4.2.1.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\b\cgrid0 For Reference Only =
-}{\f20\cgrid0 }{
\f6\fs16\cgrid0 set_fanout_load (Ambit)
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 set_fanout_load <load> <port_list>
\par }{\b\fs18\cf1\cgrid0 Ambit Description:}{\i\fs18\cgrid0 }{\cgrid0 =
The }{\f6\fs16\cgrid0 set_fanout_load }{\cgrid0 command is used to =
specify the fanout load on the ports of a cell. While port capacitance =
af
fects timing analysis, fanout loads are used to enforce the design rule =
checks.
\par }{\b\cgrid0 Arguments:}{\cgrid0=20
\par }\pard \fi720\sb120\widctlpar\adjustright {\cgrid0 Ambit =
Arguments:
\par }\pard \fi720\li720\sb120\widctlpar\adjustright {\cgrid0 =
Load;}{\i\f21\cgrid0 }{\f1\fs18\cgrid0 Total fanout load external to =
the cell.
\par }{\f6\fs16\cf1\cgrid0 port_list }{\i\f21\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 List of ports.}{\f1\fs18\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
}{\f6\fs16\cgrid0 None
\par }\pard \widctlpar\adjustright {\b\cgrid0 Attributes:}{\cgrid0 =
fanout_load_limit
\par }{\b\cgrid0 Design Database:}{\cgrid0 =20
\par }\pard \nowidctlpar\adjustright {\b Related =
Commands}{\b\f1\fs18\cf1\cgrid0 :}{\f1\fs18\cf1\cgrid0 =
set_current_module
\par }\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385970}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Fanout Load Limit (Ambit) - yes{\*\bkmkend _Toc443385970}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Fanout Load Limit
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid {Semantic =
definition: }{\cf1\cgrid0 Specifies the fanout load limit (maximum =
value) on target output ports for a within a design hierarchy. While =
port capacitance affects timing analysi
s, fanout loads are used to enforce the design rule checks. The design =
rule requirement of a maximum fanout load value is set using the global =
attribute fanout_load_limit. =20
\par }{\f20\cf1\cgrid0 This command overrides the default fanout load =
limit on specific ports set by the global attribute, =
global_}{\f6\fs16\cf1\cgrid0 fanout_load_limit}{\f20\cf1\cgrid0 .
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition, cell =
instance, or flattened cell occurrence
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Drive capability of an output port =
of a cell
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright \b\fs20\c=
grid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Fanout load limit value\cell Integer\cell >=3D 0\cell=20
The maximum number of input ports that a cell output port may =
drive\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc443385971}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
Reference - set_fanout_load_limit (Ambit){\*\bkmkend _Toc443385971}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\fs18\cf1\cgrid0 Command:}{\f20\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Syntax:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs16\cf1\cgrid0 =
set_fanout_load_limit <load port_list>
\par }\pard \sb120\nowidctlpar\adjustright {\b\cf1\cgrid0 =
Description:}{\cf1\cgrid0=20
The set_fanout_load_limit command is used to specify the fanout load =
limit (maximum value) on the ports of a cell. While port capacitance =
affects timing analysis, fanout loads are used to enforce the design =
rule checks. The design rule requireme
nt of a maximum fanout load value is set using the global attribute =
fanout_load_limit. =20
\par }{\f20\cf1\cgrid0 This command overrides the default fanout load =
limit on specific ports set by the global attribute =
}{\f6\fs16\cf1\cgrid0 fanout_load_limit}{\f20\cf1\cgrid0 .
\par }{\b\fs18\cf1\cgrid0 Arguments:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 load }{\i\f21\cf1\cgrid0 \emdash =
}{\f1\fs18\cf1\cgrid0 Fanout load limit on the ports.
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f21\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 =
Options:}{\f1\fs18\cf1\cgrid0 None
\par }{\b\fs18\cf1\cgrid0 Attributes:}{\f1\fs18\cf1\cgrid0 fanout_load_=
limit
\par }{\b\fs18\cf1\cgrid0 Design Database:
\par Related Commands:}{\f1\fs18\cf1\cgrid0 set_current_module, =
set_fanout_load
\par }{\b\fs18\cf1\cgrid0 Examples:}{\f1\fs18\cf1\cgrid0 =
}{\f6\fs16\cf1\cgrid0 set_fanout_load_limit 4 [find -port -output =
data*]}{\f20\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s5 \b\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.2.1.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Global Fanout Load Limit =
(Ambit)
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Global Fanout Load Limit
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid {Semantic =
definition: }{\cf1\cgrid0=20
Specifies a global fanout load limit (maximum value) for output ports =
for a within a design hierarchy. While port capacitance affects timing =
analysis, global fanout load limits are used to define an overall =
fanout rule.=20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Port of a cell definition, cell =
instance, or flattened cell occurrence
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Overall drive capability of output =
ports within a design hierarchy and its associated technology
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Global fanout =
load limit value\cell Integer\cell >=3D 0\cell The maximum number of =
input ports that a cell output port may drive
\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc443385972}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.1.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Number External Sinks=20
{\*\bkmkend _Toc443385972}(Ambit)
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Number External Sinks=20
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {Semantic =
definition: Specifies }{\cgrid0 that the number
of target external sink (input or bi-directional) ports are connected =
to the ports in the port list. This number is factored into the wire =
capacitance and the wire resistance estimation done for the port nets =
using the wire load models. The number extern
al sinks assertion is specified for top level input and output ports.
\par The number external sinks assertion does not add towards the total =
fanout count for Design Rule Violation(DRV). If you do not annotate =
number external sinks, then the fanout is set to be=20
a default of 1 for the port (and any other internal sink ports of the =
wire or net within the design hierarchy).=20
\par Note that with a number external sink assertion, that exact number =
is added to the count of internal sinks for the wire/net associated =
with the target port. Therefore, setting the assertion, number external =
sinks, to 1 has no effect.
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Technology definition for the =
target output ports
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell Cell must exist i
n the target design hierarchy\cell name of the cell (if the top cell) =
or cell instance\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh
\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt
\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Number of external sinks\cell Integer\cell >=3D 0\cell=20
Specifies the number of external sink ports to be associated with a =
target port for the purpose of later doing net timing calculations\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard =
\qj\sb120\widctlpar\adjustright {
\par {\listtext\pard\plain\s6 \i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.2.1.4.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {For reference only \endash=20
Set Num External Sinks (Ambit)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {\cgrid0=20
The set_num_external_sinks command can be specified on top level input =
and output ports. This command sets the constraint that the number of =
external sinks specified by the command are connected to the=20
ports in the port list. This number is factored into the wire =
capacitance and the wire resistance estimation done for the port nets =
using the wire load models.
\par It does not add towards the total fanout count for Design Rule =
Violation(DRV). If you do not ann
otate set_num_external_sinks, then the fanout is 1 for the port (and =
any other internal sinks of the wire). If you specify =
set_num_external_sinks, then you get that exact number added to the =
count of internal sinks of the wire. Therefore, setting set_num_
external_sinks 1 has no effect.
\par For more information on design rule violations, see the =
description for \ldblquote set_fanout_load\rdblquote on page 29.
\par Arguments:
\par num_sinks \emdash Number of external sinks
\par port_list \emdash List of ports
\par Options:
\par Attributes:}{
\par=20
\par {\*\bkmkstart _Toc443385974}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls53\ilvl3\outlinelevel3\adjustright \b\cgrid {
Output Port Internal Implementation Constraints{\*\bkmkend =
_Toc443385974}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart OutputPortInternal}{\*\bkmkend OutputPortInternal}
The following are definitions and constraints found at the output ports =
of the internal definition or implementation of a block that will later =
be reused as a block instance in a design hierarchy (and as an =
occurrence in the unfolded=20
design). That is, these definitions and constraints are those =
properties of an output port and possibly its associated local =
interconnect found within a design definition of a design hierarchy. =
These constraints are part of the characteristics of what=20
may or should happen at or near the output port when signals flow to =
the output port via the surrounding interconnect of the internal or =
local design definition.
\par=20
\par {\*\bkmkstart _Toc443385978}{\listtext\pard\plain\s5 \b\fs20\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls53\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\fs20=20
Drive resistance (Ambit) yes{\*\bkmkend _Toc443385978}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Drive Resistance
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0=20
Specifies the drive resistance of a target port of a cell in a =
hierarchical design. The drive resistance information is used to =
compute an offset to the arrival time of an input port, and also to =
change the slew time used
to compute the delay of a signal of the cell on an input port (sink) =
of the net. Drive resistance is only used for timing analysis and does =
not affect the electrical properties of the design.=20
\par The arrival time of a signal at the input port is modified by=20
adding the RC constant to the specified arrival time at the input port. =
The RC constant is the capacitance(C) seen at the input port multiplied =
by the Drive Resistance (R). The RC value is used as the slew value for =
the delay calculation of the next cell.
This assertion overrides the Drive Cell information per port if it is =
the last assertion that is applied. Also, if Drive Resistance is =
defined for a port, then Slew Time is ignored for that port.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Output Port of a cell definition, =
cell instance, or flattened cell occurrence port=20
\par }\pard\plain \s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390=
\adjustright \fs20\cf1\cgrid {\b Depends On\tab }{Effective resistance =
at and behind the output port that is applicable to calculating =
estimated signal delay and slew based on th
e output port driver characteristics
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC, Static Timing Analysis
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\f0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh
\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt
\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10350\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Target port name or list\cell Identifier\cell Input or =
bi-directional port\cell Identifies t
he input port on the target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Resistance =
value
\cell Ohms as float\cell Positive value\cell Specifies the resistance =
of an output port that used to calculate an estimated additional signal =
delay and value of slew\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\trowd=20
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10350\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Option\cell =
Enumerated label of=20
\ldblquote rise\rdblquote , \ldblquote fall\rdblquote , \ldblquote =
early\rdblquote , \ldblquote late\rdblquote \cell One or more values =
may be included. Values may be \{\ldblquote Rise\rdblquote and/or =
\ldblquote Fall\rdblquote \} or separately \{
\ldblquote Early\rdblquote or \ldblquote Late\rdblquote \}.\cell =
}\pard\plain \sb120\nowidctlpar\intbl\adjustright \fs20\cgrid {If =
\ldblquote }{\cf1\cgrid0 rise\rdblquote=20
, specifies that the drive resistance is applicable to only the rising =
edge transition at the input port.
\par If \ldblquote fall\rdblquote , specifies that the resistance is =
applicable only to the falling edge transition at the input port. If =
neither \ldblquote rise\rdblquote nor \ldblquote fall\rdblquote o
ptions are specified then the resistance is applied to both transitions =
at the input port.
\par If \ldblquote early\rdblquote , specifies that the drive =
resistance should be applied to the early arrival time (hold time) for =
timing analysis.
\par If \ldblquote late\rdblquote , specifies that the drive resistance =
should be applied to the late arrival time (setup time) for timing =
analysis.
\par }\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {\cell }\pard\plain \widctlpar\intbl\adjustright =
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc443385979}{\listtext\pard\plain\s6 \i\fs20 =
\hich\af0\dbch\af0\loch\f0 1.4.2.2.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\fs20\cgrid0=20
set_drive_resistance{\*\bkmkend _Toc443385979} (Ambit)
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\cf1\cgrid0 Command: }{\cf1\cgrid0 set_drive_resistance
\par }{\b\cf1\cgrid0 Syntax: }{\cf1\cgrid0 set_drive_resistance ?-rise =
| -fall? ?-early | -late? value
\par port_list
\par }{\b\cf1\cgrid0 Description: }{\cf1\cgrid0 The set_
drive_resistance command is a simpler version of the set_drive_cell =
command and can be used in many situations where the drive resistance =
can be specified. It is only used for timing analysis. It does not =
affect the electrical properties of the design. It
is used to specify the drive resistance of a cell. It computes an =
offset to the arrival time of an input and also changes the slew time =
used to compute the delay of the cell on the sink of the net.
\par The arrival time at the input port is modified by adding t
he RC constant to the specified arrival time at the input port. The RC =
constant is the capacitance(C) seen at the input port multiplied by the =
drive resistance (R). The RC value is used as the slew value for the =
delay calculation of the next cell. This co
mmand overrides the set_drive_cell command per port if it is the last =
command applied. Also, if set_drive_resistance is set for a port, =
set_slew_time is ignored for that port.
\par }{\b\cf1\cgrid0 Arguments: }{\cf1\cgrid0 value }{\i\cf1\cgrid0 =
\emdash }{\cf1\cgrid0 Resistance value.
\par port_list }{\i\cf1\cgrid0 \emdash }{\cf1\cgrid0 List of ports for =
which drive resistance is specified.
\par }{\b\cf1\cgrid0 Options: }{\cf1\cgrid0 -rise \emdash Specifies =
that the drive resistance is applicable to only the rising edge =
transition at the input port.
\par -fall \emdash Specifies that the resistance is applicable only to =
the falling edge transition at the input port. If either rise nor fall =
options are specified then the resistance is applied to both =
transitions at the input port.
\par -early \emdash Specifies that the drive resistance should be =
applied to the early arrival time (hold time) for timing analysis.
\par -late \emdash Specifies that the drive resistance should be =
applied to the late arrival time (setup time) for timing analysis.
\par Attributes
\par }{\b\cf1\cgrid0 Design Database: }{\cf1\cgrid0=20
\par }{\b\cf1\cgrid0 Related Commands: }{\cf1\cgrid0 set_drive_cell
\par set_slew_time
\par }{\b\cf1\cgrid0 Examples: }{\cf1\cgrid0 set_drive_resistance=20
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\cf1\cgrid0 [expr 3 * =
[get_cell_drive -cell IV \endash pin A] ] [-input -port * ]
\par }\pard \qj\sb120\widctlpar\adjustright {{\*\bkmkend =
_Toc432826548}{\*\bkmkend _Toc434042497}{\*\bkmkend _Toc434061598}
\par {\listtext\pard\plain\s6 \i\fs22\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4.2.2.1.2\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls53\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {For reference only \endash =
Drive Cell (Ambit)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid =
{Definition:}{\cgrid0 The set_drive_cell command i
s used to accurately model the drive capability of an external driver =
connected to the input port. It is only used for timing analysis. It =
does not affect the electrical properties of the design. This means =
that the capacitance of the output pin of the d
riving cell does not add to the total capacitance of the input port. =
It computes an offset to the arrival time of an input and also changes =
the slew time used to compute the delay of the cell on the sink of the =
net. =20
\par The offset to data_arrival_time is com
puted by taking the total delay of the cell for C seen at the input =
(not including its own C driver) and sub-tracting the total delay of =
the cell given C load of zero. The total delay means the propagation =
and transition delays, if applicable. The transit
i
on delay itself is used as the slew value for the delay calculation of =
the next cell. The library cell that drives the input of the design =
must be identified. The cell can be designated as the driving cell for =
the ports in context by using set_drive_cell=20
command. =20
\par This command overrides the set_drive_resistance command, per port =
or per net, if it is the last command applied. Also, if set_drive_cell =
is set for a port, set_slew_time is ignored for that port.
\par }\pard \qj\sb120\nowidctlpar\adjustright {\cf1\cgrid0 Arguments =
port_list }{\i\cf1\cgrid0 \emdash }{\cf1\cgrid0 List of ports driven =
by the driver cell.
\par Syntax set_drive_cell ?-early | -late? ?-cell <cell_name>? ?-cell_
\par rise <cell_name>? ?-cell_fall <cell_name> ? ?-library
\par <library_name> ? ?-library_rise <library_name>? ?-library_
\par fall <library_name>? ?-pin <pin_name>? ?-pin_rise
\par <pin_name>? ?-pin_fall <pin_name>? ?-from_pin
\par <from_pin_name> ? ?-from_pin_rise <from_pin_name>? ?-from_
\par pin_fall <from_pin_name> ? ?-source_edge_rise R|F? ?-source_
\par edge_fall R|F? <port_list>
\par }{\cgrid0 Options -early }{\i\cgrid0 \emdash }{\cgrid0 Specifies =
that the driver provides an early signal, also known as hold.
\par -late }{\i\cgrid0 \emdash }{\cgrid0 Specifies that the driver =
provides a late signal, also known as setup.
\par -cell cell_name }{\i\cgrid0 \emdash }{\cgrid0 Name of the driver =
cell that provides both a rising edge transition driver and a falling =
edge transition driver.
\par -cell_rise <cell_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the =
cell that provides a rising transition driver.
\par -cell_fall <cell_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the =
cell that provides a falling transition driver.
\par -library <library_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the =
library which contains the driving cell. This option is used if the =
same cell prov
ides both the rising and the falling edge transitions, or if different =
cells provide the rising edge and falling edge transitions but are in =
the same library.
\par -library_rise <library_name> }{\i\cgrid0 \emdash }{\cgrid0 Name =
of the library which contains the rising edge transition driver.
\par -library_fall <library_name> }{\i\cgrid0 \emdash }{\cgrid0 Name =
of the library which contains the falling edge transition driver.
\par -pin <pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the output =
port of the driver cell that drives the signal at the input port of the =
design. This option is required if there=20
are multiple output ports on the driver. If there is only one out-put =
port on the driver cell, use of this option is not necessary.
\par -pin_rise <pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of the =
output port of the driver cell which provides the rising edge =
transition drive to the input port of the design.
\par -pin_fall <pin_name>}{\i\cgrid0 \emdash }{\cgrid0 Name of the =
output port of the driver cell which provides the falling edge =
transition drive to the input port of the design.
\par -from_pin <from_pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name of =
the input port of the driver cell which has an arc
to the output port of the driver cell which is con-nected to the input =
port of the design. This option is required if there are multiple =
timing arcs in the driver cell from its input ports to its output =
ports. It assumes that the same timing arc between=20
the input port and the output port of the driver cell is driving both =
the rising edge transi-tion and the falling edge transition on the =
input port of the design.
\par -from_pin_rise <from_pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name =
of the input port of the driver cell with the controlling timing arc to =
the output port of the driver cell that provides the rising edge =
transition drive to the input port of the design.
\par -from_pin_fall <from_pin_name> }{\i\cgrid0 \emdash }{\cgrid0 Name =
of the input port of the driver cell with the controlling timing arc to =
the output port of the driver cell that provides the falling edge =
transition drive to the input port of the design.
\par -source_edge_rise R | F }{\i\cgrid0 \emdash }{\cgrid0 Specifies =
whether the rising (R) edge or the falling edge (F) at the =
from_pin_name is controlling the rising edge transition at the input =
port of the design.
\par -source_edge_fall R | F }{\i\cgrid0 \emdash }{\cgrid0 Specifies =
whether the rising edge (R) or the falling edge (F)at the from_pin_name =
is controlling the falling edge transition at the input port of the =
design.=20
\par }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par=20
\par }}
--Boundary_(ID_C/fzpNlfRENfxf0q4MSbXg)--