A different teleconferencing system will be used for
this meeting only. Call 800-862-4522, then 1, 3000.
The meeting name is DCWG, and the meeting id is 3294.
Agenda
------
- Discuss case sensitivity, name mapping issues
Attached are excerpts from some internal Cadence documentation
on the issues.
VHDL Normal Names
-----------------
VHDL normal identifiers are case insensitive. This means that the
identifier AbC and the identifier abc are equivalent, and refer to
the same object. VHDL normal identifiers can contain letters, digits,
or the underscore character. The first letter must be a character.
All alphanumeric characters are allowed as VHDL normal identifiers.
The only symbol that is allowed is the underscore. The space is not
allowed.
VHDL Escaped Names
------------------
VHDL escaped identifiers are case sensitive, unlike normal VHDL names.
Escaped identifiers always begin and end with a backslash ( \ ). This
means that the identifier \AbC\ and the identifier \aBc\ refer to two
different objects. An identifier in the VHDL normal name space and the
same identifier in the VHDL escaped name space do not represent the same
object. For example, the VHDL identifiers abc and \abc\ refer to two
different objects. To embed a backslash in an escaped identifier, use
double backslashes. If the original identifier was in the VHDL escaped
form even though it was legal in the VHDL normal form, it needs to be
returned to the escaped form, not the normal form. For example, \abc\
maps to CDBA ESC_abc,and it maps back to \abc\ in VHDL. All alphanumeric
characters and symbols, as well as spaces, are allowed as VHDL escaped
identifiers.
Verilog Normal Names
--------------------
Verilog normal identifiers are case sensitive. This means that
the identifier AbC and the identifier abc refer to two different
objects. Verilog normal identifiers might contain letters, digits,
the underscore character, and the dollar sign ($). The first
character cannot be a digit or a dollar sign ($). All letters
and digits are allowed as Verilog normal identifiers. The space
is not allowed.
Verilog Escaped Names
---------------------
Verilog escaped identifiers always begin with a backslash (\) and
terminate with a space. Verilog escaped identifiers are case sensitive.
This means that the identifier \AbC and the identifier \aBc refer to
two different objects. Although any identifier can be escaped, only
those identifiers that might not be represented in the Verilog normal
name space due to character restrictions or keywords need to be escaped.
An identifier in the Verilog normal name space and the exact same
identifier in the Verilog escaped name space represent the same object.
For example, the Verilog identifiers abc and \abc refer to the same
object. All alphanumeric characters and symbols are allowed in Verilog
escaped identifiers.
What Differences Exist Between Name Spaces?
Keywords The string "and" is a keyword in Verilog and VHDL,
while "process" is a keyword in VHDL but not in Verilog.
Syntax and Many name spaces have an alternative way to include
Characters characters in names that would otherwise be illegal. In
VHDL, \a+b*\ is a legal identifier because the backslashes
( \ ) escape the characters that are otherwise illegal.
A normal Verilog name can contain a dollar sign ( $ ),
but a VHDL name cannot unless it is escaped.
Keywords Not Allowed as VHDL Normal Identifiers
-----------------------------------------------
abs component guarded nor record then
access configuration if not register to
after constant impure null reject transport
alias disconnect in of rem type
all downto inertial on report unaffected
allow element inout open return units
and else is or rol until
architecture elseif label others ror use
array end library out select variable
assert entity linkage package severity wait
attribute exit literal port signal when
begin file loop postponed shared while
block for map private sla with
body function mod procedure sll xnor
buffer generate nand process sra xor
bus generic new pure srl
case group next range subtype
Keywords Not Allowed as Verilog Identifiers
-------------------------------------------
always end initial parameter small trior
and endattribute inout pmos specify trireg
assign endcase input posedge specparam use
attribute endmodule integer primitive strength vectored
begin endfunction join pull0 strong0 wait
buf endprimitive large pull1 strong1 wand
bufif0 endspecify macromodule pulldown supply0 weak0
bufif1 endtable medium pullup supply1 weak1
case endtask module rcmos table while
casex event nand reg task wire
casez for negedge release time wor
cmos force nmos repeat tran xnor
deassign forever nor rnmos tranif0 xor
default fork not rpmos tranif1
defparam function notif0 rtran tri
disable highz0 notif1 rtranif0 tri0
edge highz1 or rtranif1 tri1
else if output scalared triand
Thanks,
Mark