The full DCDL definition will have many more commands and options, but
hopefully this subset will allow us to demonstrate the basics of how
DCDL will be used. I've enclosed some possible additional commands
and options at the end.
The notation conventions follow the BuildGates strawman; we'll
probably have to revise them to be more IEEE compatible.
Notation Conventions
-abc specifies a required parameter
<abc> specifies an argument of a given type
a | b select either the a option or the b option
?<ab> | <de>? select one or none of the specified options within
the delimiters
{a b} a list containing elements a and b. The curly braces
are required in pure DCDL, but DCDL commands embedded
in a TCL script may use double quotes or refer to
a variable containing a list instead.
Proposal for the DAC demo subset
--------------------------------
1. Units
These statements must appear before any other dcd statements
dcd::units
?-time <multiplier>?
?-capacitance <multiplier>?
?-resistance <multiplier>?
?-voltage <multiplier>?
?-temperature <multiplier>?
2. Clock
dcd::waveform
-name <waveform_name>
-period <period>
-edges { <lead> <trail> }
dcd::clock
-waveform <waveform_name>
<pin_list>
3. Arrival times
I've listed two forms here for specifying values. In
the first form, it takes at least two commands to specify
all four values (early/late, lead/trail). In the second
form, -time, you can specify all four values at once.
In another Cadence constraint language, we only used -time
and adopted the convention that '*' indicates unspecified
values. For example, -time {1 2 * 4}.
We need to decide whether DCDL should be based on the
first form, the second form, or both.
dcd::data_arrival_time
?-waveform <waveform_name>?
?-lead | -trail?
?
?-early | -late? ?-rise <rise_time>? ?-fall <fall_time>?
|
-time { <early_rise> <late_rise> <early_fall> <late_fall> }
?
<pin_list>
4. Required times
dcd::data_required_time
?-target | -source? /* only -target supported for DAC */
?-waveform <waveform_name>?
?-lead | -trail?
?
?-early | -late? ?-rise <rise_time>? ?-fall <fall_time>?
|
-time { <early_rise> <late_rise> <early_fall> <late_fall> }
?
<pin_list>
5. False paths
dcd::disable
?-library <library_name>?
-cell <cell_name>
?-arcs <from_pin to_pin>?
dcd::false_path
?-from <pin_list>?
?-through <pin_list>?
?-to <pin_list>?
?-early | -late?
6. Multi-cycle paths
dcd::multi_cycle_path
?-target | -source? /* only -source supported for DAC */
?-from <pin_list>
?-through <pin_list>?
?-to <pin_list>?
?-early | -late?
<cycle_value> /* only integer values supported for DAC */
7. Drive strength
dcd::drive_resistance
?-rise | -fall?
<resistance_value>
<port_list>
8. External load
dcd::external_capacitance
<capacitance_value>
<port_list>
9. Wire load model (WLM) selection
dcd::wire_load_model
?-library <library_name>?
<wire_load_model_name>
?<instance_list>? /* omit for top instance; must omit for DAC */
10. Operating conditions
dcd::operating_conditions
?-process <value>?
?-voltage <value>?
?-temperature <value>?
Proposal for additional commands and options
that aren't part of DAC subset
--------------------------------------------
1. dcd::clock
-waveform <waveform_name>
?-invert?
<pin_list>
2. dcd::clock_arrival_time
?
?-early | -late?
?-lead <lead_time>?
?-trail <trail_time>?
|
?-time { <early_lead_time> <late_lead_time>
<early_trail_time> <late_trail_time> }?
?
<pin_list>
3. dcd::clock_insertion_delay
?
?-early | -late?
?-lead <lead_time>?
?-trail <trail_time>?
|
?-time { <early_lead_time> <late_lead_time>
<early_trail_time> <late_trail_time> }?
?
<pin_list>
4. dcd::clock_required_time
?-target | -source?
?-waveform <waveform_name>?
?
?-early | -late?
?-lead <lead_time>?
?-trail <trail_time>?
|
?-time { <early_lead_time> <late_lead_time>
<early_trail_time> <late_trail_time> }?
?
<pin_list>
5. dcd::drive_resistance
?
?-rise | -fall? ?-early | -late? <resistance_value>
|
{ <early_rise> <late_rise> <early_fall> <late_fall> }
?
<port_list>
6. dcd::internal_capacitance_limit
<capacitance_value>
<port_list>
7. dcd::operating_conditions
?-library <library_name>?
?-name <oc_name>?
?-process <value>?
?-voltage <value>?
?-temperature <value>?
?<instance_list>?
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com