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Sixth IEEE/DATC Electronic Design Processes Workshop
April 28-30, 1999
Monterey Beach Hotel, Monterey, CA
http://edp99.ece.utexas.edu
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Online Registration: https://secure.computer.org/conf/EDP/register.htm
Hotel Information: www.montereybeachhotel.com
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EDP will provide a forum for a cross-section of the design community to
discuss state-of-the-art electronic design processes and CAD methodologies.
Specific goals of EDP 99 are to:
* Identify and evaluate key trends and known best practices that are
driving changes in the design process, with respect to technology and
the business model.
* Identify and evaluate the common barriers to product delivery with
respect to design processes.
* Identify and prioritize issues requiring further research in
development, deployment, and assessment of design processes and the
tools to support them.
* Review and update the "rolling roadmap" developed at earlier workshops
and disseminate findings to the design community at-large.
Dr. Naresh K. Sehgal Prof. Margarida F. Jacome
Workshop Design Technology, Intel University of Texas at Austin
co-chairs: Corp. jacome@ece.utexas.edu
naresh.k.sehgal@intel.com http://horizon.ece.utexas.edu/~jacome
(408) 765-4179 (512) 471-2051
Organizing Naresh Sehgal (Intel) Margarida F. Jacome (U. Texas
committee: David Hathaway (IBM) Austin)
Steve Grout (Sematech)
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Program
Wednesday, April 28, 1999
6:00 PM - 8:00 PM Reception
Thursday, April 29, 1999
9:00 AM - 9:15 AM Welcome
9:15 AM - 10:00 AM Keynote - The Top Ten Problems with Design Flows
for Bleeding Edge Designs, Gary Smith, Dataquest,
San Jose, CA
10:00 AM - 10:30 AM Break
Session 1: High Level Design
10:30 AM - 11:00 AM The Support and Management of Dynamic Conceptual
Design Processes, Jingyan Zuo, Carnegie Mellon
University, Pittsburgh, PA, and Stephen W. Director,
University of Michigan, Ann Arbor, MI
11:00 AM - 11:30 AM Embedded Systems hw/sw Codesign: Opportunities and
Requirements, William Fornaciari, Politecnico di
Milano, Milano, Italy
11:30 AM - 12:00 PM Towards a Common Hardware-Software Object Model
(CHSOM), Hugo A. Andrade, National Instruments
Corporation, Austin, TX, and Margarida F. Jacome,
University of Texas at Austin
12:00 PM - 1:30 PM Lunch
Session 2: Methodology Improvements
1:30 PM - 2:00 AM Future Methodologies, Paul Weil, Weil Cad
Consulting
2:00 PM - 2:30 PM Timing Driven Chip Hierarchical Design System
(TDD/CHDS) - A Plan for Meeting the Coming Design
Process Crisis, Steve Grout, Phil Fisher, Amrish
Chockhavatia, SEMATECH, Austin, TX, and Don
Cottrell, SI2, Austin, TX
2:30 PM - 3:00 PM Assisting Early Design Space Exploration for
IP-Based Designs, Helvio P. Peixoto and Margarida
F. Jacome, University of Texas at Austin
3:00 PM - 3:30 PM Break
Session 3: Tool Environments
3:30 PM - 4:00 AM The UMLe: A VLSI CAD/EDA Learning Environment,
Jose' A. D. F. Lima, Universidade do Minho,
Portugal
4:00 PM - 4:30 PM True plug & play, speaker TBD
4:30 PM - 5:00 PM Architectural Considerations for Integrated
Incremental Design Tools, David Hathaway, IBM
Corporation, Essex Junction, VT
6:30 PM - 8:30 PM Banquet - speaker, Charlie Rosenthal, How well
we have been solving the EDA problems?
Friday, April 30, 1999
Session 4: Application Methodologies
8:30 AM - 9:00 AM The Delay and Power Calculation System, Harold
Reindel, James Engel, IBM Corporation, Essex
Junction, VT, and H. John Beatty, IBM Corporation,
Hopewell Junction, NY
9:00 AM - 9:30 AM Design Automation for ATPG of IBM ASICs, Pamela
Gillis, Elizabeth Bouldin, and Andrew Ferko, IBM
Microelectronics, Essex Junction, VT
9:30 AM - 10:00 AM The Design Constraints Description Language (DCDL),
Mark Hahn, Cadence Design Systems, San Jose, CA
10:00 AM - 10:30 AM Break
Session 5: More Methodology Improvements
10:30 AM - 11:00 AM Expected Design Process improvements of the System
Level Design Language (SLDL), speaker TBD
11:00 AM - 11:30 PM Using Front-End Planning to Avoid Back-End
Problems, Dwight Hill, Synopsys, Mt. View, CA
11:30 PM - 12:00 PM It's the Methodology, Stupid!, Pran Kurup and Taher
Abbasi, ByteK Designs, Inc., Palo Alto, CA
12:00 PM - 1:00 PM Luncheon & Planning session for next EDP workshop
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