DC-WG: MIPS R4000 Assertions

Bob Dilly (dilly@btv.ibm.com)
Mon, 05 Apr 1999 16:45:00 -0400

Although the starting point was a really simple set of assertions,
a number don't fit the proposed DAC subset. Also, a good number of
the "interesting" statements don't get exercised...

Anyway, for what its worth, here's what I ended up with by starting
with BuildGates.

Bob

# ------------------------------------------------------------------------
# Purpose: mR4000 assertions culled from BuildGates script.
# (Since this is the DCDL stawman)
#
# Uses "find" function to get lists of ports.
# ------------------------------------------------------------------------

# ------------------------------------------------------------------------
# BuildGates synthesis stuff:
#
#syn# read_verilog ./mR4000.v
#syn# do_build_generic
# ------------------------------------------------------------------------

# ------------------------------------------------------------------------
# Not supported in proposed DAC demo subset:
# ------------------------------------------------------------------------
#bg# set_current_module mR4000
#bg# set_top_timing_module mR4000
#bg# set_wire_load_mode top
#bg# set_global slew_propagation_mode critical_slew
#bg# set_clock_propagation propagated

# ------------------------------------------------------------------------
# Choose appropriate wireload model based on library type:
# .lib set_wire_load 10KCELLS_6LM
# DPCM set_wire_load 10kCells
# ------------------------------------------------------------------------
#bg# set_wire_load 10kCells
dcd::wire_load_model 10kCells
dcd::wire_load_model -library IBM_SA27_SC 10kCells

#bg# set_clock master_clk -waveform {0 9.0} -period 18.0
#bg# set_clock_arrival_time -clock master_clk -r 0.0 -f 9.0 Clk
dcd::waveform -name master_clk -period 18.0 -edges {0 9.0}
dcd::clock -waveform master_clk Clk

# ------------------------------------------------------------------------
# Looks like DCDL syntax requires explicit -late and -early flags.
# ------------------------------------------------------------------------
#bg# set_data_arrival_time -clock master_clk 2.0 [find -port -input *]
dcd::data_arrival_time -waveform master_clk -late 2.0 -early 2.0 [find -port -input *]

#bg# set_data_required_time -clock master_clk -rise -fall 9.0 [find -port -output *]
dcd::data_required_time -waveform master_clk -rise 9.0 -fall 9.0 [find -port -output *]

# ------------------------------------------------------------------------
# Not supported in proposed DAC demo subset:
# ------------------------------------------------------------------------
#bg# set_slew_time -clock master_clk 0.1 [find -port -input *]
#bg# set_slew_time -clock master_clk -pos 0.1 clk
#bg# set_slew_time -clock master_clk -neg 0.1 clk

#bg# set_port_capacitance 0.2 [find -port -output *]
dcd::external_capacitance 0.2 [find -port -output *]

#syn# do_optimize -effort high

# ------------------------------------------------------------------------
# Sample "find" results from BuildGates
#
# find -port -input *
# 429382 431926 431766 431750 431686 431590 431494 431398 431302 431206 431110 .....
# ------------------------------------------------------------------------
# find -port -output *
# 446934 446470 432982 432822 432806 432790 432774 432758 432742 432726 432710 .....
# ------------------------------------------------------------------------