Attendees:
  Mark Hahn, Cadence (Chair)
  Tom Dewey, Mentor
  Ed Martinage, Cadence
  Greg Schulte, Cadence
  Vikas Sharma, IBM
New action items:
      Who         When     What
      ----------  ------   --------
 1.   Mark        4/27     Send example of how the DAC demo subset
                           would be extended with typical values
 2.   Mark        4/27     Send modified version of processor design
                           to IBM
Open action items:
      Who         When     What
      ----------  ------   --------
 1.   Mark        4/20     Close on DAC demo participation from
                           Synplicity, Altera
 2.   Bob         4/20     Determine whether an NDA is required for the
                  -> 4/27  library data
 3.   Mark        3/2      Add operating conditions to the taxonomy
                  -> 3/30
                  -> 4/13
                  -> 5/4
Closed action items:
      Who         When     What
      ----------  ------   --------
 1.   Mark        4/20     Provide a list of BuildGates commands that
                           accept min/max values for best case, worst
                           case operating conditions
Next Meeting:
  The next meeting will be a teleconference on 4/27
  from 9-11 am (PDT).
Details:
  1. Review action items
     No progress on the library NDA question, because Bob is
     on vacation.
     Synplicity and Altera will decide whether to participate
     by the end of April.  Synopsys has indicated that they will
     not participate directly, but they don't see any problem with
     demonstrating translators between DCDL and the Synopsys design
     constraints format, if the translator is developed by a company
     licensed under the TAP-in program.  Cadence is considering whether
     there is enough time to do this.
  2. Discuss DAC demo
     There are still some problems in translating the IBM library to
     TLF.  These will be revisited when Bob returns.
     IBM has a translator from Einstimer commands to PrimeTime commands,
     but this is for a previous version of Einstimer and would not be
     easy to to adapt for the demo.
     Velocity can consume the Synopsys design constraints format, but
     doesn't have plans to read the DAC DCDL subset.  We talked about
     whether it would make sense to include Velocity in the demo and
     agreed that doing so doesn't demonstrate additional support for
     DCDL.
     We talked about typical values, as used in delay calculation for
     SDF min:typ:max triplets.  Mark proposed adding a -typical flag
     and expanding the number of possible values from 4 to 6 for
     environment conditions that may be used in SDF.  Vikas had some
     concerns about Einstimer's ability to support this, and Mark will
     send an example to clarify.
     Einstimer uses absolute value adjustments for multi-cycle path
     constraints, rather than clock period multiples as in DCDL.
     Vikas is working through issues in converting between the two.
     Cadence has implemented most of the first draft of the DCDL subset
     in both BuildGates and Pearl.  Waiting for the TLF to test Pearl
     on the demo design.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com