-- --PART-BOUNDARY=.1990524191433.ZM8091.Cadence.COM Content-Type: text/plain; charset=us-asciiAttached is an update to the golden DCDL script for the demo addressing two changes: - the setting for the process derating point - the syntax for the multi_cycle_path
I've also updated the file version number in the comments to be 0.95.
Thanks, Mark
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com--PART-BOUNDARY=.1990524191433.ZM8091.Cadence.COM Content-Description: Text Content-Type: text/plain ; name="embedded_constraints.dcd" ; charset=us-ascii Content-Disposition: attachment ; filename="embedded_constraints.dcd" X-Zm-Content-Name: embedded_constraints.dcd
# ------------------------------------------------------------------------ # Pure DCDL script for DAC '99 demo, ASIC design flow # Version 0.95 # ------------------------------------------------------------------------
# ------------------------------------------------------------------------ # Units used in this file # - time is in ns # - capacitance is in pF # - voltage is in volts # ------------------------------------------------------------------------ units -time 1.0E-9 units -capacitance 1.0E-12 units -voltage 1.0
# ------------------------------------------------------------------------ # Use the same wire load model for the whole design # ------------------------------------------------------------------------ wire_load_model -library IBM_SA27_SC 10KCELLS_5LM
# ------------------------------------------------------------------------ # Clock definitions # ------------------------------------------------------------------------ waveform -name master_clk -period 18.0 -edges {0 9.0} waveform -name inverted_clk -period 18.0 -edges {1.0 10.0} -inverted
clock -waveform master_clk Clk
# ------------------------------------------------------------------------ # Input arrival times # ------------------------------------------------------------------------
# expanded form data_arrival_time -waveform master_clk -lead -early -rise 6.0 \ [find -port MemData*]
data_arrival_time -waveform master_clk -lead -late -rise 7.0 \ [find -port MemData*]
data_arrival_time -waveform master_clk -lead -early -fall 6.5 \ [find -port MemData*]
data_arrival_time -waveform master_clk -lead -late -fall 7.5 \ [find -port MemData*]
# compact form data_arrival_time -waveform master_clk -lead { 6.0 7.0 6.5 7.5 } \ [find -port MemData*]
# ------------------------------------------------------------------------ # Output required times # ------------------------------------------------------------------------ data_required_time -target -waveform master_clk -lead \ { -2.0 3.0 -1.5 3.5 } \ [find -port ReadAdd*]
data_required_time -target -waveform master_clk -trail \ { 0.5 1.5 2.0 2.2 } \ [find -port WriteAdd*]
data_required_time -target -waveform master_clk -lead \ { -2.0 3.0 -1.5 3.5 } \ [find -port WriteData*]
data_required_time -target -waveform inverted_clk -lead \ { -2.0 5.0 -1.5 4.5 } \ { MemWrite MemRead }
# ------------------------------------------------------------------------ # Input slew (transition) times # ------------------------------------------------------------------------ slew_time -rise 0.1 [all_inputs] slew_time -fall 0.2 [all_inputs] slew_time 0.1 Clk
# ------------------------------------------------------------------------ # Output capacitances # ------------------------------------------------------------------------ external_capacitance 0.2 [all_outputs]
# ------------------------------------------------------------------------ # False paths # ------------------------------------------------------------------------ false_path -from Reset
# ------------------------------------------------------------------------ # Multi-cycle paths # ------------------------------------------------------------------------ multi_cycle_path -source -to { MemWrite MemRead } -early 1 multi_cycle_path -source -to { MemWrite MemRead } -late 2
--PART-BOUNDARY=.1990524191433.ZM8091.Cadence.COM Content-Description: Text Content-Type: text/plain ; name="expanded_constraints.dcd" ; charset=us-ascii Content-Disposition: attachment ; filename="expanded_constraints.dcd" X-Zm-Content-Name: expanded_constraints.dcd
# ------------------------------------------------------------------------ # Pure DCDL script for DAC '99 demo, ASIC design flow # Version 0.95 # ------------------------------------------------------------------------
# ------------------------------------------------------------------------ # Units used in this file # - time is in ns # - capacitance is in pF # - voltage is in volts # ------------------------------------------------------------------------ units -time 1.0E-9 units -capacitance 1.0E-12 units -voltage 1.0
# ------------------------------------------------------------------------ # Use the same wire load model for the whole design # ------------------------------------------------------------------------ wire_load_model -library IBM_SA27_SC 10KCELLS_5LM
# ------------------------------------------------------------------------ # Clock definitions # ------------------------------------------------------------------------ waveform -name master_clk -period 18.0 -edges {0 9.0} waveform -name inverted_clk -period 18.0 -edges {1.0 10.0} -inverted
clock -waveform master_clk Clk
# ------------------------------------------------------------------------ # Input arrival times # ------------------------------------------------------------------------
data_arrival_time \ -waveform master_clk -lead \ -early -rise 6.0 \ { MemData[0] MemData[1] MemData[2] MemData[3] \ MemData[4] MemData[5] MemData[6] MemData[7] \ MemData[8] MemData[9] MemData[10] MemData[11] \ MemData[12] MemData[13] MemData[14] MemData[15] \ MemData[16] MemData[17] MemData[18] MemData[19] \ MemData[20] MemData[21] MemData[22] MemData[23] \ MemData[24] MemData[25] MemData[26] MemData[27] \ MemData[28] MemData[29] MemData[30] MemData[31] }
data_arrival_time \ -waveform master_clk -lead \ -late -rise 7.0 \ { MemData[0] MemData[1] MemData[2] MemData[3] \ MemData[4] MemData[5] MemData[6] MemData[7] \ MemData[8] MemData[9] MemData[10] MemData[11] \ MemData[12] MemData[13] MemData[14] MemData[15] \ MemData[16] MemData[17] MemData[18] MemData[19] \ MemData[20] MemData[21] MemData[22] MemData[23] \ MemData[24] MemData[25] MemData[26] MemData[27] \ MemData[28] MemData[29] MemData[30] MemData[31] }
data_arrival_time \ -waveform master_clk -lead \ -early -fall 6.5 \ { MemData[0] MemData[1] MemData[2] MemData[3] \ MemData[4] MemData[5] MemData[6] MemData[7] \ MemData[8] MemData[9] MemData[10] MemData[11] \ MemData[12] MemData[13] MemData[14] MemData[15] \ MemData[16] MemData[17] MemData[18] MemData[19] \ MemData[20] MemData[21] MemData[22] MemData[23] \ MemData[24] MemData[25] MemData[26] MemData[27] \ MemData[28] MemData[29] MemData[30] MemData[31] }
data_arrival_time \ -waveform master_clk -lead \ -late -fall 7.5 \ { MemData[0] MemData[1] MemData[2] MemData[3] \ MemData[4] MemData[5] MemData[6] MemData[7] \ MemData[8] MemData[9] MemData[10] MemData[11] \ MemData[12] MemData[13] MemData[14] MemData[15] \ MemData[16] MemData[17] MemData[18] MemData[19] \ MemData[20] MemData[21] MemData[22] MemData[23] \ MemData[24] MemData[25] MemData[26] MemData[27] \ MemData[28] MemData[29] MemData[30] MemData[31] }
# ------------------------------------------------------------------------ # Output required times # ------------------------------------------------------------------------ data_required_time \ -target -waveform master_clk -lead \ { -2.0 3.0 -1.5 3.5 } \ { ReadAdd[0] ReadAdd[1] ReadAdd[2] ReadAdd[3] \ ReadAdd[4] ReadAdd[5] ReadAdd[6] ReadAdd[7] \ ReadAdd[8] ReadAdd[9] ReadAdd[10] ReadAdd[11] \ ReadAdd[12] ReadAdd[13] ReadAdd[14] ReadAdd[15] \ ReadAdd[16] ReadAdd[17] ReadAdd[18] ReadAdd[19] \ ReadAdd[20] ReadAdd[21] ReadAdd[22] ReadAdd[23] \ ReadAdd[24] ReadAdd[25] ReadAdd[26] ReadAdd[27] \ ReadAdd[28] ReadAdd[29] ReadAdd[30] ReadAdd[31] }
data_required_time \ -target -waveform master_clk -trail \ { 0.5 1.5 2.0 2.2 } \ { WriteAdd[0] WriteAdd[1] WriteAdd[2] WriteAdd[3] \ WriteAdd[4] WriteAdd[5] WriteAdd[6] WriteAdd[7] \ WriteAdd[8] WriteAdd[9] WriteAdd[10] WriteAdd[11] \ WriteAdd[12] WriteAdd[13] WriteAdd[14] WriteAdd[15] \ WriteAdd[16] WriteAdd[17] WriteAdd[18] WriteAdd[19] \ WriteAdd[20] WriteAdd[21] WriteAdd[22] WriteAdd[23] \ WriteAdd[24] WriteAdd[25] WriteAdd[26] WriteAdd[27] \ WriteAdd[28] WriteAdd[29] WriteAdd[30] WriteAdd[31] }
data_required_time \ -target -waveform master_clk -lead \ { -2.0 3.0 -1.5 3.5 } \ { WriteData[0] WriteData[1] WriteData[2] WriteData[3] \ WriteData[4] WriteData[5] WriteData[6] WriteData[7] \ WriteData[8] WriteData[9] WriteData[10] WriteData[11] \ WriteData[12] WriteData[13] WriteData[14] WriteData[15] \ WriteData[16] WriteData[17] WriteData[18] WriteData[19] \ WriteData[20] WriteData[21] WriteData[22] WriteData[23] \ WriteData[24] WriteData[25] WriteData[26] WriteData[27] \ WriteData[28] WriteData[29] WriteData[30] WriteData[31] }
data_required_time \ -target -waveform inverted_clk -lead \ { -2.0 5.0 -1.5 4.5 } \ { MemWrite MemRead }
# ------------------------------------------------------------------------ # Input slew (transition) times # ------------------------------------------------------------------------ slew_time -rise 0.1 \ { MemData[0] MemData[1] MemData[2] MemData[3] \ MemData[4] MemData[5] MemData[6] MemData[7] \ MemData[8] MemData[9] MemData[10] MemData[11] \ MemData[12] MemData[13] MemData[14] MemData[15] \ MemData[16] MemData[17] MemData[18] MemData[19] \ MemData[20] MemData[21] MemData[22] MemData[23] \ MemData[24] MemData[25] MemData[26] MemData[27] \ MemData[28] MemData[29] MemData[30] MemData[31] }
slew_time -fall 0.2 \ { MemData[0] MemData[1] MemData[2] MemData[3] \ MemData[4] MemData[5] MemData[6] MemData[7] \ MemData[8] MemData[9] MemData[10] MemData[11] \ MemData[12] MemData[13] MemData[14] MemData[15] \ MemData[16] MemData[17] MemData[18] MemData[19] \ MemData[20] MemData[21] MemData[22] MemData[23] \ MemData[24] MemData[25] MemData[26] MemData[27] \ MemData[28] MemData[29] MemData[30] MemData[31] }
slew_time 0.1 Clk
# ------------------------------------------------------------------------ # Output capacitances # ------------------------------------------------------------------------ external_capacitance 0.2 \ { ReadAdd[0] ReadAdd[1] ReadAdd[2] ReadAdd[3] \ ReadAdd[4] ReadAdd[5] ReadAdd[6] ReadAdd[7] \ ReadAdd[8] ReadAdd[9] ReadAdd[10] ReadAdd[11] \ ReadAdd[12] ReadAdd[13] ReadAdd[14] ReadAdd[15] \ ReadAdd[16] ReadAdd[17] ReadAdd[18] ReadAdd[19] \ ReadAdd[20] ReadAdd[21] ReadAdd[22] ReadAdd[23] \ ReadAdd[24] ReadAdd[25] ReadAdd[26] ReadAdd[27] \ ReadAdd[28] ReadAdd[29] ReadAdd[30] ReadAdd[31] \ WriteAdd[0] WriteAdd[1] WriteAdd[2] WriteAdd[3] \ WriteAdd[4] WriteAdd[5] WriteAdd[6] WriteAdd[7] \ WriteAdd[8] WriteAdd[9] WriteAdd[10] WriteAdd[11] \ WriteAdd[12] WriteAdd[13] WriteAdd[14] WriteAdd[15] \ WriteAdd[16] WriteAdd[17] WriteAdd[18] WriteAdd[19] \ WriteAdd[20] WriteAdd[21] WriteAdd[22] WriteAdd[23] \ WriteAdd[24] WriteAdd[25] WriteAdd[26] WriteAdd[27] \ WriteAdd[28] WriteAdd[29] WriteAdd[30] WriteAdd[31] \ WriteData[0] WriteData[1] WriteData[2] WriteData[3] \ WriteData[4] WriteData[5] WriteData[6] WriteData[7] \ WriteData[8] WriteData[9] WriteData[10] WriteData[11] \ WriteData[12] WriteData[13] WriteData[14] WriteData[15] \ WriteData[16] WriteData[17] WriteData[18] WriteData[19] \ WriteData[20] WriteData[21] WriteData[22] WriteData[23] \ WriteData[24] WriteData[25] WriteData[26] WriteData[27] \ WriteData[28] WriteData[29] WriteData[30] WriteData[31] \ MemWrite MemRead }
# ------------------------------------------------------------------------ # False paths # ------------------------------------------------------------------------ false_path -from Reset
# ------------------------------------------------------------------------ # Multi-cycle paths # ------------------------------------------------------------------------ multi_cycle_path -source -to { MemWrite MemRead } -early 1 multi_cycle_path -source -to { MemWrite MemRead } -late 2
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# ------------------------------------------------------------------------ # Pure DCDL script for DAC '99 demo, ASIC design flow # Version 0.95 # # Operating conditions definition only # ------------------------------------------------------------------------
operating_conditions -temperature 90 operating_conditions -process 1.0 operating_conditions -voltage 2.0
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