The contents of the following proposal has been discussed
within Cadence, but not with the rest of the group. Hopefully
we can quickly agree on how to resolve the ambiguities.
1. set_data_arrival_time specifies a waveform edge and
a quadruplet of values (early rise, late rise,
early fall, late fall). The values represent the
earliest and latest times at which a transition can
occur at the specified ports or pins, as a positive
offset from the reference waveform edge time.
These are referred to as "clock edge relative" times.
2. set_data_required_time is also clock edge relative,
but both the early and late values represent a negative
offset from the reference waveform edge. The offsets
should reflect the hold and setup times of the register(s)
driven by the specified ports/pins, as well as the partial
path delays from the ports/pins to the register(s). In full
DCDL, the insertion delay and uncertainty of the clock path
to the target register(s) will be specified in a separate
command, so they should not be included in the
set_data_required_time values.
3. The <cycle_offset> value of multi_cycle_path represents
the total number of cycles used for the setup or hold
check, rather than the number of additional cycles.
Increasing values of <cycle_offset> result in looser
constraints for both setup and hold (-late and -early).
It may be clearer to name this parameter <num_cycles>.
For example, multi_cycle_path ... {1 2} specifies
that the hold check should use 1 cycle instead of the
default of 0 cycles, while the setup check should use
2 cycles instead of the default of 1 cycle.
Let's discuss this in the teleconference this week.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com