Subject: DC-WG: 3/28 meeting minutes
From: Mark Hahn (mhahn@cadence.com)
Date: Tue Apr 04 2000 - 08:17:47 PDT
Meeting minutes from the 3/28/00 DC-WG teleconference
-----------------------------------------------------
Attendees:
Mark Hahn, Cadence
Tom Dewey, Mentor
Bob Dilly, IBM
Jim Engel, IBM
John Paul, IBM
Vikas Sharma, IBM
New action items:
Who When What
---------- ------ --------
1. Tom 4/4 Update the spec with changes
2. Tom 4/4 Find out who else will be using the
standards booth
3. Bob 4/4 Investigate whether a pure EDIF name
space in DCDL would be sufficient for
IBM's needs
Open action items:
Who When What
---------- ------ --------
1. Bob 3/28 Create a block diagram that shows the
-> 4/4 relationship between the TCL interpreter,
DCDL TCL cmds, and the reference parser
Closed action items:
Who When What
---------- ------ --------
1. Tom 3/28 Update the spec with changes
Next Meeting:
The next meeting will be a teleconference on 4/11/00
from 10-12 am (PDT)
Details:
1. DAC planning
Tom will follow up with Dennis Brophy to find out what other
groups will be doing in the standards booth. Our concern is
that, given the time constraints, we don't want to set the
expectation that the DCDL demo will be the centerpiece (or only
piece) of the booth. We particularly don't want to be the
only exhibit in a fairly large booth.
2. Discuss EDIF option for design_name_space
The first question was whether EDIF is used frequently
enough in design flows today to justify the inclusion;
IBM uses it fairly widely in their flow.
We were concerned that most tools have complicated
options for reading and writing EDIF, because the native
EDIF name space is fairly primitive. When mapping between
EDIF and other languages, escaped names etc. lead to "misuse"
of the EDIF name space, and the extra options control how
to interpret names that don't conform properly.
3. Timing commands
Vikas is working on extending the reference parser to cover
additional commands, and had a number of questions. We agreed
to accelerate discussion on these commands, and that based
on the discussion, Vikas would submit proposals for updating
the spec, which Tom will incorporate, assuming that the proposals
are ok pending later review.
The false_path command should have -from_waveform and
-to_waveform options.
There was some discussion about clock roots versus waveforms.
The advantage of separating the concepts lies in defining virtual
clocks that are used as a reference for arrival and required times
but aren't actually provided to the module currently being described.
There should be -pin_load and -wire_load options to the external_load
command.
Waveform edge times may be negative numbers.
3. Discuss current_scope command, scoping theory
We discussed relative path names and agreed that DCDL should
require a leading hierarchical delimiter at the start of fully
qualified path names. If a leading hierarchical delimiter is
specified, then the name is interpreted with respect to the top
level cell in the design regardless of what the current scope
is. If a leading hierarchical delimiter isn't specified, then
the name is interpreted as relative to the current scope.
The hierarchical delimiter is defined by the design_name_space,
but the rule about having a leading hierarchical delimiter in
fully qualified names is specific to DCDL.
Thanks,
Mark
-- Mark Hahn phone: (408) 428-5399 Senior Architect fax: (408) 428-5959 Cadence Design Systems email: mhahn@cadence.com
This archive was generated by hypermail 2b28 : Tue Apr 04 2000 - 08:21:26 PDT