DC-WG: DCDL Spec 7.6.16.5 Example Changes


Subject: DC-WG: DCDL Spec 7.6.16.5 Example Changes
From: dilly@us.ibm.com
Date: Tue May 09 2000 - 12:16:13 PDT


Folks-
Here's a shot at adding some text about the defaults and replicating the
"inverted" example without actually using the -inverted flag. I was
thinking
about spelling out a second version of the first example, i.e.

waveform -name master_clk -period 18.0

which is equivalent given the defaults. Actually, if I read the v 0.2.8
spec
correctly, the following would also be equivalent:

waveform -name master_clk -edges {0 9.0}

Don't know if that's instructional........

Anyway, a shot at the waveform examples section follows....

    Regards...... Bob

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7.6.16.5 Examples

waveform -name master_clk -period 18.0 -edges {0 9.0}

The preceding example defines a waveform called master_clk with a period of
18 ns (units set to ns in a pre-ceding command) with edges at 0 and 9 ns.
The
-edges flag is not strictly required in this example because the defaults
of a
50% duty-cycle and the leading edge at time 0.

waveform -name inverted_clk -period 18.0 -edges { 1.0 10.0} -inverted
waveform -name inverted_clk -period 18.0 -edges {11.0 19.0}

The preceding examples defines a clock that is inverted. Both examples
describe
the same waveform. The -inverted flag is replaced in the second example by
adding half the period to each edge in the first example.
-----------------------------------------------------------------------

--
Bob Dilly
IBM Microelectronics
Department G46V - M/S 863K
Burlington, VT 05452-4299
- - - - - - - - - - - - - - - - - - - -
(802)-769-7786  (tie 446)



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