RE: [$ieee-1850] Assertion-Control System Tasks

Ben,

You are essentially proposing the addition of a capability to control PSL execution from a testbench. We could consider that as a possible extension to the standard.

However, if we do so, we must consider all flavors of PSL, not just Verilog. That is, whatever control capability we define would have to work in VHDL 1076, Verilog 1364, and SystemVerilog 1800 testbenches, and perhaps others (e.g., if we define a SystemC flavor of PSL). To do that, I think we would need to define a set of abstract control operations and then specify how those control operations are invoked in each language flavor - e.g., through the use of tasks in Verilog, or procedures in VHDL, or whatever. Someone might even argue that we should define standard bindings for these control operations for tcl and perl as well.

One question to ask here is what goals this extension would be intended to achieve. Are we just looking for flexible control over assertion execution? (If so, perhaps this would be best left to proprietary solutions that would evolve rapidly via competition in the marketplace.) Or are we looking for portability of testbenches? (If so, what other components of the testbench need to be standardized to ensure portability of the whole?) We may need to answer this question before we can productively consider such an extension.

In the mean time, I'll add an extension request for an abstract API definition plus language bindings for control of assertion language execution in simulation.

Regards,

Erich

| -----Original Message-----
| From: owner-ieee-1850@eda.org
| [mailto:owner-ieee-1850@eda.org] On Behalf Of ben cohen
| Sent: Monday, November 15, 2004 11:47 AM
| To: Cindy Eisner
| Cc: ieee-1850@eda.org
| Subject: Re: [$ieee-1850] Assertion-Control System Tasks
|
| Cindy,
| Considering the vunit, we can define a set of reserved
| procedures or tasks called "asserton, assertoff, assertkill".
| We could also state
| that they would have significance only in simulation. Currently a
| user can either use the vunit, or puts PSL within HDL as
| comments, and vendors have adopted the pragma "psl". I see
| no reason why this cannot be maintained. For example:
| module testbench;
| ....
| always @ (posedge clk) begin
| if(in_setup_mode)
| // psl assertoff;
| else if (done_setup_mode)
| // psl asserton;
| end
| endmodule
|
| On Mon, 15 Nov 2004 10:52:31 +0200, Cindy Eisner
| <eisner@il.ibm.com> wrote:
| >
| >
| > ben,
| >
| > >SystemVerilog Assertions has Assertion-Control System
| Tasks to enable
| > >/ disable the turning ON /OFF of assertions. This is very useful.
| > >PSL does not have that feature.
| > >Do we want to add this feature?
| >
| > maybe, once we have made the decision to define the
| embedding of psl
| > within an hdl. until the embedding of psl within an hdl is
| defined in
| > the standard, the question is meaningless - where would
| such controls go?
| >
| > cindy.
| >
| > --------------------------------------------------------------------
| > Cindy Eisner
| > Formal Methods Group
| > IBM Haifa Research Laboratory
| > Haifa 31905, Israel
| > Tel: +972-4-8296-266
| > Fax: +972-4-8296-114
| > e-mail: eisner@il.ibm.com
| >
| > ben cohen <hdlcohen@gmail.com>@eda.org on 13/11/2004 00:59:30
| >
| > Please respond to ben cohen <hdlcohen@gmail.com>
| >
| > Sent by: owner-ieee-1850@eda.org
| >
| >
| > To: ieee-1850@eda.org
| > cc:
| >
| >
| > Subject: [$ieee-1850] Assertion-Control System Tasks
| >
| > SystemVerilog Assertions has Assertion-Control System Tasks
| to enable
| > / disable the turning ON /OFF of assertions. This is very useful.
| > PSL does not have that feature.
| > Do we want to add this feature?
| >
| > In SystemVerilog:
| > assert_control_task ::= assert_task [ ( levels [ ,
| > list_of_modules_or_assertions ] ) ] ;
| > assert_task ::=
| > $asserton
| > | $assertoff
| > | $assertkill
| >
| >
| ----------------------------------------------------------------------
| > ---- Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
| > http://www.vhdlcohen.com/ vhdlcohen@aol.com Upcoming book:
| > SystemVerilog Assertions Handbook, ISBN 0-9705394-7-9
| >
| > Author of following textbooks:
| > * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,
| > 2004 isbn 0-9705394-6-0
| > * Real Chip Design and Verification Using Verilog and VHDL,
| 2002 isbn
| > 0-9705394-2-8
| > * Component Design by Example ", 2001 isbn 0-9705394-0-1
| > * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
| > 0-7923-8474-1
| > * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
| > 0-7923-8115
| >
| ----------------------------------------------------------------------
| > -----
|
|
Received on Mon Nov 15 10:00:51 2004