[$ieee-1850] Assertion-Control System Tasks

SystemVerilog Assertions has Assertion-Control System Tasks to enable
/ disable the turning ON /OFF of assertions. This is very useful.
PSL does not have that feature.
Do we want to add this feature?

In SystemVerilog:
assert_control_task ::= assert_task [ ( levels [ ,
list_of_modules_or_assertions ] ) ] ;
assert_task ::=
               $asserton
              | $assertoff
              | $assertkill

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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Upcoming book: SystemVerilog Assertions Handbook, ISBN 0-9705394-7-9

Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,
2004 isbn 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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Received on Fri Nov 12 15:00:55 2004