Harry, The LRM makes no mention on when signals used in the assertions are sampled and evaluated. VHDL has the notion of delta time, thus assertions evaluated at clock edges do not interfere with signal updates. SystemVerilog has the concept of regions, preponed for the sampling of signals and observe for the evaluation of the assertions. Verilog has the blocking nonblocking concept and misuse of these can lead to errors if the evaluation of the assertions is not done correctly. Question: Should the PSL LRM address the issue of when are signals used in assertions samples and when they are evaluated? Should this be a tool issue, rather thatn an LRM? I lean more of an LRM issue, otherwise there could be interoperability issues. Thanks, Ben -------------------------------------------------------------------------- Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 http://www.vhdlcohen.com/ ben_ f rom _abv-sva.org * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9 * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ---------------------------------------------------------------------------Received on Sun Mar 13 22:49:10 2005
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