Fw: Request for feedback: adding vector types to STANDARD

Folks,

Following is my posting requesting fedback on adding vector types to
STANDARD.

Cheers,

PA

> Folks,
>
> The IEEE VHDL Working Group is considering a proposal to add vector
> types to the package STANDARD in the next revision of the language.
> We would like your feedback on the issue.
>
> Currently, package STANDARD defines types STRING as a vector of
> CHARACTER elements, and BIT_VECTOR as a vector of BIT elements. The
> proposal is to define vector types for BOOLEAN, INTEGER, REAL and
> TIME. Users have commented that these types would be useful for
> verification models, among other applications.
>
> REAL_VECTOR is defined in STANDARD in the VHDL-AMS standard. Adding
> it to the base VHDL standard would enhance portability of packages
> between the two languages.
>
> The down side is that there is potential to break existing models.
> Suppose, for example, a model declares INTEGER_VECTOR in a package
> MY_TYPES, and then uses the package throughout the model with use
> clauses. If we add INTEGER_VECTOR to STANDARD, which is used in all
> design units, we would now have the same name used from two different
> packages. The VHDL rules covering visibility of names would cause
> neither version to be visible. Models suffering this effect would have
> to be edited to remove the declaration in the user-defined package.
>
> We would appreciate feedback from users on their preferred option:
> adding the proposed types to STANDARD, or not adding the types to
> avoid breaking legacy models. Rationale for your preference would be
> helpful. You can either reply to this newsgroup or to me directly.
> I'll summarize the feedback on this group.
>
> Many thanks.
>
> Cheers,
>
> Peter Ashenden
>
> --
> Dr. Peter J. Ashenden peter@ashenden.com.au
> Ashenden Designs Pty. Ltd. www.ashenden.com.au
> PO Box 640 Ph: +61 8 8339 7532
> Stirling, SA 5152 Fax: +61 8 8339 2616
> Australia Mobile: +61 414 70 9106
>
>
Received on Wed Dec 15 17:35:09 2004