ISAC: call for vote on IR2040

Please vote on this IR.

Also, most of you haven't yet voted on the six IRs I sent out a few days
ago.

Chuck

VHDL Issue Number: 2040

Language_Version: VHDL-2002
Classification: Language Definition Problem
Summary: Problems with OTHERS in aggregates
Relevant_LRM_Sections: 3.2.1.1, 7.3.2.2
Related_Issues:
Key_Words_and_Phrases: aggregates, OTHERS, individual subelement association
Authors_Name: James Unterburger
Authors_Phone_Number: 503.685.0860
Authors_Fax_Number: 503.685.0921
Authors_Email_Address: jamesu@model.com
Authors_Affiliation: Model Technology
Authors_Address1: 8005 SW Boeckman Road
Authors_Address2: Wilsonville, OR 97070
Authors_Address3:

Current Status: Submitted

Superseded By:

------------------------
Date Submitted: 12 August 2004
Date Analyzed: 06 October 2004
Author of Analysis: Ajayharsh Varikat
Revision Number: 02
Date Last Revised: 13 December 2004

Description of Problem
----------------------
Consider the following code fragment:

ENTITY e IS
       GENERIC ( n1:natural := 1, n2:natural := 16);
       PORT( P1: IN bit_vector, P2: IN bit_vector(1 TO 16),
             P3: IN bit_vector(n1 TO n2);
END ENTITY e;

ENTITY top
...
SIGNAL sig1:bit_vector(1 TO 8);
...

label1: e PORT MAP(
        P1(1 TO 8) => (OTHERS => '1'), P1(9 TO 16) => sig1,
        P2(1 TO 8) => (OTHERS => '1'), P2(9 TO 16) => sig1,
        P3(1 TO 8) => (OTHERS => '1'), P3(9 TO 16) => sig1);
...

Are any of these port maps legal?

The applicable statement seems to be item a) in section 7.3.2.2 (Array
aggregates) which states that an array aggregate with an OTHERS choice
must appear only in one of the following contexts: "a) As an actual
associated with a formal parameter or formal generic declared to be of
a constrained array subtype (or subelement thereof)..."

There seem to be at least three problems here.

First, item a) does not mention formal ports. This is probably an
oversight in the 1987 to 1993 transition, when it became legal to associate
a globally static expression with a port of mode IN.

Second, the term "subelement thereof" prohibits slices. This was probably
an oversight and the word "subelement" should probably be "member".

Third, the formal is required to be declared with a constrained subtype.
Since P1 is not constrained, this example appears to be illegal.

However, in all the above cases the applicable range is "obvious" and
most users would think that the first two examples are legal, and,
perhaps, the third case is legal, but a check must be performed that
the subtype of P3 actually has index range 1 TO 16 (16 DOWNTO 1 would
not be legal because the slices of P3 have direction TO).

Another basic problem is that slices have no subtypes but they have
ranges, which ought to be applicable. Similarly, section 3.2.1.1
(Index constraints and discrete ranges) gives rules for determining
index ranges for unconstrained parameters whose elements are
associated individually, but does not say that these index ranges
create a subtype.

These rules needlessly restrict the use of OTHERS in aggregates.

Proposed Resolution
-------------------
Allow OTHERS in array aggregates associated with slice-of-formal in an
individual association.

VASG-ISAC Analysis & Rationale
------------------------------

Item (a) in section of 7.3.2.2 of the LRM states:
  
    a) As an actual associated with a formal parameter or formal generic
       declared to be of a constrained array subtype (or subelement thereof)

This item does not list a formal port association as a valid context in
which an aggregate with an others clause may appear. It is most likely
that this section was overlooked when static expressions were allowed as
actuals in port maps (VHDL93).

By mentioning only subelements, the current wording disallows an others
clause to be associated with a slice of the formal. This restriction
appears to be unintentional. The term member should have been used
instead of subelement.

Also, the restriction that the formal has to be of a constrained array subtype
can be relaxed. It is sufficient that the range of the formal expression in
the association element be determinable independent of the actual expression.

Item (d) in this section also has similar issues.

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Change item (a) in section 7.3.2.2 of the LRM to the following:

  a) As an actual associated with a formal parameter, formal generic or
     formal port (or member thereof), and either
       1) the formal is declared to be of a constrained array subtype, or
       2) the formal designator is a slice name

Change item (d) in this section to:

  d) As a value expression in an assignment statement, where the target is a
     declared object (or member thereof), and either
     1) the subtype of the target is a constrained array subtype, or
     2) the target is a slice name

Also change the second sentence of the fourth paragraph in this section from

     If the aggregate appears in one of the contexts in the preceding list,
     then the direction of the index subtype of the aggregate is that of
     the corresponding constrained array subtype;...

to

     If the aggregate appears in one of the contexts in the preceding list,
     then the direction of the index subtype of the aggregate is that of
     the corresponding constrained array subtype or that of the range of
     the corresponding slice name, as appropriate; ...
Received on Thu Dec 16 12:42:26 2004