Attached are the minutes. Please let me know of any mistakes, etc. The minutes are also available on the website. Also attached is the list of VHDL93 IRs and the VHDL2002 status of those which were resolved at the last meeting. Chuck Swart Minutes of ISAC meeting held via telecom on 31 August 2005 Present: Larry Soule, Chuck Swart, Ajay Verikat Absent: Peter Ashenden, Jim Lewis, Deepak Pant Next Meeting: Thursday October 6, 2005, 7 pm Pacific Daylight Time (Friday October 7, 2005, 2 am GMT) TOPIC: Status of Web Based IR System The system is available at: https://bugzilla.mentor.com Please register there so that you can login. Currently there is only a test project available and only one bugzilla issue. The issue, #1, is a summary of the requirements for an on-line system, and contains Peter's suggested mapping between VASG IR status and Bugzilla states. Chuck will be adding more stuff to this website. TOPIC: IR 2071 Indexed name in case expression The submitter correctly complains about the following wording for case statements: "If the expression is of a one-dimensional character array type, then the expression must be one of the following: ... -- An indexed name whose prefix is one of the members of this list and whose indexing expressions are locally static expressions" The requirement that the indexing expressions be locally static makes sense for slices but is overly restrictive for indexed names, since the size information comes from the (locally static) index subtype. ACTION: All to review. We'll discuss this at our next meeting. TOPIC: IR 2072 allow static operations on "ranges" At first glance, this request seems a little strange. It is clearly an enhancement request, but some analysis should be done to determine whether or not there are technical issues. It seems that what the submitter wants are operations between a range and a scalar. Does he also want operations between two ranges? If so, what is the interpretation when the ranges have different directions. Also, what effect would this extension have on an already-complicated grammar? ACTION: All to check for subtle problems. TOPIC: IR 2073 Index constraints and discrete range conversions from universal_integer The submitter claims, correctly, that the code: for i in 0 to 2 ** N -1 loop... is technically illegal because the implicit conversion from universal integer to INTEGER applies only to numeric literals or attributes (or, presumable division of two values of a give physical type). This rule makes for i in 1 to 10 loop ... legal, but for i in -1 to 10 loop illegal. This problem was recognized in Ada, and was solved by adding new types (root_integer and root_real) and by changing the overload resolution rules to favor these new types in ambiguous cases. ACTION: Chuck to analyze Categorization of old IRs: It was agreed that (eventually) we will move open VHDL93 IRs into the VHDL2002 database. Chuck will maintain a list showing the status of VHDL93 IRs. Status 1002 Open Ambiguity as to when parameter subtype indications are elaborated. 1003 Open Non-commutative and non-associative resolution functions are a source of non-determinism 1004 Enhancement-Analysis needed Are deferred constants still deferred after their full declaration? 1008 Resolved Function NOW is undefined during static elaboration. 1009 Open Unclear context of evaluation for formal part of block map aspects. 1013 Open Reference to a generate loop parameter in a configuration is unclear 1014 Open The LENGTH attribute is ill-defined. 1017 Open Why must a name in a wait stmt. sens. list be static? 1019 ??Compare with 2028 The signal updating steps of the simulation cycle is incorrect. 1024 Open VPI Issue 20 -- Primary units with same name Analysis of VHDL93 IRs for VHDL2002 1002 Open Ambiguity as to when parameter subtype indications are elaborated. 1003 Open Non-commutative and non-associative resolution functions are a source of non-determinism 1004 Enhancement-Analysis needed Are deferred constants still deferred after their full declaration? 1008 Resolved Function NOW is undefined during static elaboration. 1009 Open Unclear context of evaluation for formal part of block map aspects. 1013 Open Reference to a generate loop parameter in a configuration is unclear 1014 Open The LENGTH attribute is ill-defined. 1017 Open Why must a name in a wait stmt. sens. list be static? 1019 ??Compare with 2028 The signal updating steps of the simulation cycle is incorrect. 1024 Open VPI Issue 20 -- Primary units with same name 1000 Accumulated typographical and terminology errors. 1001 Entity aspect in default binding indication is unclear. 1005 Unclear requirements on prefix in predefined attribute names. 1006 Parentage checks are difficult to verify during static model elaboration. 1007 Can a range constraint in a type declaration use 'RANGE? 1010 Overloaded convertible operands make type analysis very difficult. 1011 Enumeration literals, physical units, and library names cannot be attributed. 1012 It is unclear how Physical Literals of type TIME should be treated when checking for conformance. 1015 The note illustrating the equivalent sequence of declarations for a constrained array type definition is 1016 LRM definition of block statements is ambiguous. 1018 What does "reference" mean? 1020 The 'note' implies that predefined attributes of the actual will not be visible on the formal. 1021 Constrained arrays with negative index bounds are difficult to declare. 1022 A subtype Delay would aid VHDL definition and use. 1023 VPI Issue 2 -- Specifications applying to 0 entities 1025 Checking the target type of an aggregate signal assignment 1026 Glossary refers to old "size constraint" in entry for "constraint." 1027 REVERSERANGE should be a keyword in the language. 1028 Is the entity identifier directly visible in architecture bodies and configuration declarations? 1029 What should happen when there is a port clause in a block statement but no port map clause? 1030 Imprecise wording and inconsistent presentation order. 1031 Can targets be in the form of nested aggregates? 1032 May analyzers make non-locally static checks? 1033 Attributes cannot be specified in package bodies. 1034 Qualified expression checks may be too restrictive. 1035 Rules for non-local access to signals and variables in functions are too restrictive. 1036 Integer subtypes & operations 1038 The definitions of A'LEFT, A'RIGHT, A'HIGH, A'LOW, A'RANGE, and A'REVERSE_RANGE are ill-defined when 1039 May subelements and slices of procedure signal parameters be individually driven? 1040 Resolved composite signals are difficult to associate. 1041 Implicit signals are not objects. Moreover, they may not be signals. 1042 Missing sentence for variable assignment aggregate target. 1043 User defined attribute on function name 1044 Definition of 'HIGH and 'LOW in a null range 1045 Qualified expressions lead to lexical ambiguity 1046 Unclear definition of "resolved signal." 1047 VPI Issue 10 -- Entity class type vs. subtype 1048 Deferred constant reference before complete definition. 1049 When is an entity bound to the library it references? 1050 Visibility outside of design units is not well-defined. 1051 Direct visibility rules for USE clauses are incomplete and confusing. 1052 Rules for others in aggregates are incomplete 1053 This IR number (1053) was allocated but not needed. 1054 Short-circuit operators don't when called as functions 1055 Reading predefined signal attributes of subprogram signal parameters within the subprograms. 1056 Certain error requirements are not well-defined. 1057 Expanded names are not allowed in extended regions. 1058 What use are LINKAGE ports? 1059 What is the allowed use of others in record aggregates? 1060 A'LEFT's result type is anomalously described. 1062 Can a resolution function return an unconstrained array? 1063 Scope and visibility rules for predefined attributes are unclear. 1064 Passiveness of processes is not analysis-time computable. 1066 Conversion function definition assumes different types. 1068 When do buffer ports have sources? 1069 Mod and rem are ill-defined when they return zero. 1070 VPI Issue 14 -- Prefixes in USE clauses 1071 The bounds of array aggregates are ill-defined. 1072 Does the elaboration of a process statement create a process? 1073 The meaning of a qualified expression is in dispute 1074 Interpretation of overloaded name prefixes is unclear. 1075 Self-referential access types are not prohibited. 1076 Applicability of resolution functions is still unclear. 1077 Out ports cannot drive buffer ports. 1078 Memory leak and portability issue with TEXTIO 1079 Conflicting rules for direction of concatenation 1081 Expression elaboration with impure functions 1082 Implicit conversion of a universal real expression 1083 Pureness of function ENDFILE 1085 "Staticness" of the predefined attribute INSTANCE_NAME 1086 Use of character literal or operator symbol in alias 1088 Problems with physical mapping of libraries 1089 Visibility problem with components and USE clauses 1090 Do library clauses extend from entities to architectures? 1091 Group constituent names cannot have signatures. 1092 Must a selected name in a use clause denote anything? 1093 Replacement characters (from Ada) complicate parsing. 1094 Bad wording for individual association for subprograms. 1095 Are time literals with real numeric parts exact? 1096 Entity aspect poorly defined for incremental binding. 1097 Why do primary unit names in secondary units differ? 1098 Can variable parameters be left unassociated or not? 1104 Inconsistent, overly restrictive subtype checks. 1105 The elaboration of group declarations is not defined. 1106 Accumulated problems with unclear wording. 1107 Postponed process behave illogically at initialization. 1108 The subtype of a deferred constant may not always be deduced during analysis time. 1109 The term "named entity" it not defined. 1110 The term "object" is not well-defined. 1111 Is a user-defined attribute an object? 1112 Need to disallow conversion function signal parameters. 1114 LRM wording doesn't account for separators. 1115 Should subtype and constraint checks really be made when the driver takes on the value of a signal? 1116 implicit signals in guard expression (via port maps) 1117 Problem with Composite Resolved Signal 1118 Group constituent can't be user-defined attribute name. 1119 LRM is not clear as to when the wait statement condition clause is evaluated in a postponed process. 1120 Inconsistency about the mode of formal parameters of class file. 1121 Meaning of a changed value for reals is not clear 1122 Default binding text and examples disagree 1123 Simulation cycle does not account for processes resuming after expiration of the timeout interval 1124 Are all actuals evaluated in incremental binding?Received on Thu Sep 1 14:15:41 2005
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