ISAC: New IR 2074 Problem with direct/select visibility in formal part

This IR is very technical, so you will probably need to spend some time 
understanding the issue.
Different implementations disagree on this.

Chuck Swart

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VHDL Issue Number:      2074

Language_Version:       VHDL-2002
Classification:         Language Definition Problem
Summary:                Problem with direct/select visibility in formal part
Relevant_LRM_Sections:  4.3.2.2, 10.3
Related_Issues:         0006
Key_Words_and_Phrases:  
Authors_Name:           Chuck Swart
Authors_Phone_Number:   503.685.0846
Authors_Fax_Number:     503.685.0921
Authors_Email_Address:  cswart@model.com
Authors_Affiliation:    Model Technology
Authors_Address1:       8005 SW Boeckman Road
Authors_Address2:       Wilsonville, OR 97070
Authors_Address3:   

Current Status:         Submitted

Superseded By:

------------------------
Date Submitted:         12 September 2005
Date Analyzed:
Author of Analysis:
Revision Number:        0
Date Last Revised:      12 September 2005

Description of Problem
----------------------
Consider the following two VHDL code fragments:

A)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL; -- X01 becomes visible as a subtype
ENTITY e1...
...
ARCHITECTURE a1 OF e1 IS
    COMPONENT c1 IS
       PORT(X01: IN std_logic);
BEGIN
    instance1: c1 PORT MAP ( X01(X01)=> s1);
END a1;

B)

PACKAGE p2 IS
        constant X01: integer := 1;
        subtype bv1 is bit_vector(1 TO 1);
END p2;

LIBRARY ieee;
USE work.p2.ALL; --X01 and bv1 become visible
ENTITY e2...
...
ARCHITECTURE a2 OF e2 IS
    COMPONENT c1 IS
       PORT(X01: IN bv1);
BEGIN
    instance1: c1 PORT MAP ( X01(X01)=> s2);
END a2;

Are either of these legal VHDL?

In example A) there are two possible interpretations:

1. The leftmost X01 is a type mark (with direct visibility) and the
X01 inside the parentheses is a formal designator. This expression is
legal.  

2. The leftmost X01 is a port name (with visibility by selection)
indexed by a subtype, which in this case is illegal.

In example B) there are also two possible interpretations, with the
legal/illegal cases reversed from example A) with respect to direct
visibility and visibility by selection:

1. The leftmost X01 is a constant name (with direct visibility) and
the expression inside the parentheses is a port name. This construct
is clearly illegal.

2. The entire term is a formal designator, which reduces to an indexed
name.  The leftmost X01 is a port name (with visibility by selection)
and the X01 inside the parentheses is an index expression.

The grammar allows
    formal_part ::=
                formal_designator
               |<function>_name ( formal_designator)
               | type_mark ( formal_designator )

The name of the formal designator is visible by selection while the
name of the type_mark (and the index expression in example B) are
directly visible.

So the question reduces to what visibility rules are used to analyze:

   X01(X01)

which can be interpreted syntactically as either type_mark (
formal_designator) or simple formal_designator?

Given the visibility rules of 10.3, it is hard to tell if directly
visible names take priority over names visible by selection, or
vice-versa. If direct visibility has priority then interpretation 1
applies to both examples, making example A) legal and example B)
illegal.  If selected visibility has priority, then interpretation 2
applies, making example B) legal and example A) illegal.

If one were to argue that interpretation 1 applies to example A) and
interpretation 2 applies to example B) then the visibility rules would
be context dependent (or even more context dependent than current
rules).

The syntactic ambiguity in the formal_part rule is the major area (if
not the only area) in which the rules for direct visibility conflict
with those for visibility by selection.  The closest analogy is the
potential conflict between selected names and expanded names described
in IR0006. This conflict is resolved by adopting the expanded name
interpretation.

I believe that different simulators interpret the two test cases in
different ways, so this issue should be resolved to improve
portability of the language.

Proposed Resolution
-------------------
 
Adopt a rule stating that in formal parts selected names hide directly
visible names ( or vice-versa). This would make both examples illegal.
Other solutions are possible, but the important thing is to not make
the visibility rules context sensitive. In particular, interpretations
A 1 and B 2 should not both be legal.

VASG-ISAC Analysis & Rationale
------------------------------
TBD

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


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