-------------BEGINNING OF IR---------------- VHDL Issue Number: 2097 Language_Version VHDL-2002 Classification Language Definition Problem Summary Operations with Array aggregates Relevant_LRM_Sections Related_Issues Key_Words_and_Phrases Authors_Name Jim Lewis Authors_Phone_Number 503-590-4787 Authors_Fax_Number Authors_Email_Address jim@synthworks.com Authors_Affiliation SynthWorks Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 13 June 2006 Date Analyzed: Author of Analysis: Revision Number: 1 Date Last Revised: Description of Problem ---------------------- The following code is a desirable hardware coding style, however, currently I have an issue with it in that some synthesis implementations accept it and others don't. signal ASel, BSel : std_logic; signal Y, A, B : std_logic_vector(7 downto 0) ; Y <= (A and (A'range => ASel)) or (B and (B'range => BSel)) ; It would be helpful to know if one or the other is correct. Proposed Resolution ------------------- TBD VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR----------------Received on Thu Sep 7 19:02:07 2006
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