-------------BEGINNING OF IR---------------- VHDL Issue Number: 2105 Language_Version VHDL-2002 Classification Language Modeling Enhancement or Deficiency Summary Can't declare an alias of a character literal without using expanded name Relevant_LRM_Sections 4.3.3, 6.1 Related_Issues Key_Words_and_Phrases alias, character literal Authors_Name Peter Ashenden Authors_Phone_Number +61 414 709 106 Authors_Fax_Number Authors_Email_Address peter@ashenden.com.au Authors_Affiliation Ashenden Designs Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 7 December 2006 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- The syntax rules prevent a character literal being used by itself as the name in an alias declaration. For example, it is not legal to write alias low is '0'[return bit]; The rule for name in 6.1 allows a simple name or an operator symbol, but not a character literal. The above would have to be written using an expanded name, such as alias low is STANDARD.'0'[return bit]; since the suffix of an expanded name can be a character literal. Similarly, the following is illegal: type T is ('a', 'b', 'c'); alias 'A' is 'a'[return T]; Assuming this was in an enclosing regional named R, the alias would have to be written as alias 'A' is R.'a'[return T]; Proposed Resolution ------------------- Augment the BNF rule for name in 6.1 to include character_literal as an alternative. This would mirror other places where simple_name and operator_symbol are alternatives for a designator (such as in the entity tag of an attribute specification). VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR----------------Received on Thu Dec 7 18:06:37 2006
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