2105 Submitted Chuck Can't declare an alias of a character literal without using expanded name 2106 Submitted Desire preprocessor (macro/ifdef) support in VHDL 2107 Submitted Editorial process dropped a \ from extended identifier example these have been added to the website -------------BEGINNING OF IR---------------- VHDL Issue Number: 2105 Language_Version VHDL-2002 Classification Language Modeling Enhancement or Deficiency Summary Can't declare an alias of a character literal without using expanded name Relevant_LRM_Sections 4.3.3, 6.1 Related_Issues Key_Words_and_Phrases alias, character literal Authors_Name Peter Ashenden Authors_Phone_Number +61 414 709 106 Authors_Fax_Number Authors_Email_Address peter@ashenden.com.au Authors_Affiliation Ashenden Designs Authors_Address1 Authors_Address2 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 7 December 2006 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- The syntax rules prevent a character literal being used by itself as the name in an alias declaration. For example, it is not legal to write alias low is '0'[return bit]; The rule for name in 6.1 allows a simple name or an operator symbol, but not a character literal. The above would have to be written using an expanded name, such as alias low is STANDARD.'0'[return bit]; since the suffix of an expanded name can be a character literal. Similarly, the following is illegal: type T is ('a', 'b', 'c'); alias 'A' is 'a'[return T]; Assuming this was in an enclosing regional named R, the alias would have to be written as alias 'A' is R.'a'[return T]; Proposed Resolution ------------------- Augment the BNF rule for name in 6.1 to include character_literal as an alternative. This would mirror other places where simple_name and operator_symbol are alternatives for a designator (such as in the entity tag of an attribute specification). VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR---------------- -------------BEGINNING OF IR---------------- VHDL Issue Number: 2106 Language_Version VHDL-2002 Classification Language Modeling Enhancement or Deficiency Summary Desire preprocessor (macro/ifdef) support in VHDL Relevant_LRM_Sections None. Related_Issues Key_Words_and_Phrases macro, preprocessor, ifdef Authors_Name Andrew Leaver Authors_Phone_Number 408-544-7209 Authors_Fax_Number Authors_Email_Address aleaver@altera.com Authors_Affiliation Altera Corp. Authors_Address1 101 Innovation Dr Authors_Address2 San Jose, CA Authors_Address3 95134 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 1 December 2006 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- VHDL has no standard macro preprocessor and no ifdef for conditional compilation. The lack of an ifdef/endif is the most common complaint. VHDL users can use M4 or CPP, but the lack of standardization makes it difficult to ship VHDL code that uses conditional compilation to other users. The conditional generate statement already in VHDL does not solve this problem as it cannot be applied to ports and other structures. Proposed Resolution ------------------- As the VHDL-200X standard already is planning to use ` as a compiler directive (for `protect), it would make sense to adopt the `define, `undef `ifdef, `else, `elsif, `endif, `ifndef from the Verilog 2001 standard, and later minor extensions in the SV standard. Either the CPP or M4 macro languages would also be acceptable. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR---------------- -------------BEGINNING OF IR---------------- VHDL Issue Number: 2107 Language_Version VHDL-2002 Classification LRM Examples, Notes and Appendices Summary Editorial process dropped a \ from extended identifier example Relevant_LRM_Sections 13.3.2 Extended Identifiers, examples Related_Issues Note that this was correct in 1993 and 2000-D3 revisions and seemed to have changed in the 2002 revision. Key_Words_and_Phrases Authors_Name Jim Lewis Authors_Phone_Number 503-590-4787 Authors_Fax_Number Authors_Email_Address jim@synthworks.com Authors_Affiliation SynthWorks VHDL Training Authors_Address1 11898 SW 128th Ave Authors_Address2 Tigard, OR 97223 Authors_Address3 Current Status: Submitted Superseded By: ------------------------ Date Submitted: 6 December 2006 Date Analyzed: Author of Analysis: Revision Number: 0 Date Last Revised: Description of Problem ---------------------- \BUS \bus\ -- Two different identifiers, neither of which is -- the reserved word bus. Proposed Resolution ------------------- \BUS\ \bus\ -- Two different identifiers, neither of which is -- the reserved word bus. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR----------------Received on Thu Dec 7 20:14:36 2006
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