Re: ISAC: New IR 2109

From: Jim Lewis <Jim_at_.....>
Date: Thu Feb 01 2007 - 17:54:32 PST
I agree with Peter's assessment.

 >  variable available : boolean := true;
Hopefully we can add some sort of signal or
event here and can avoid a spin loop.

Cheers,
Jim

> Folks,
> 
> I just had a quick look over this IR, and see that it relates to the issues
> of channels and interfaces that we've been canvassing in the VHDL-TC. The
> submitter is looking to use protected types for a form of interprocess
> communication (IPC). There are a whole bunch of different IPC mechanisms,
> such as sempahores of different flavours and FIFOs queues, that embody both
> abstract communication and synchronization. The synchronization aspects
> involve waiting on one one or more conditions. This area has been well
> explored and reported in the literature on concurrent programming and
> operating systems.
> 
> The protected type mechanism that we included in VHDL-2000 was based on
> Hoare monitors, but it only included the aspect of mutual exclusion on
> method entry. Hoare monitors also involve declaring condition variables on
> which a monitor can wait. While waiting, the caller relinquishes mutex,
> allowing another monitor call to proceed. That call can affect state to make
> the condition true, thus reenabling the suspended caller.
> 
> Assuming a lot of semantics, the submitter's semaphore type could be
> expressed as
> 
>   type boolean_semaphore is protected
>     procedure lock;
>     procedure free;
>   end protected boolean_semaphore;
> 
>   type boolean_semaphore is protected body
>     variable available : boolean := true;
>     procedure lock is
>     begin
>       while not available loop
>         wait until available;
>       available := false;
>     end procedure lock;
>     procedure free is
>     begin
>       available := true;
>     end procedure free;
>   end protected body boolean_semaphore;
> 
> This issue needs a lot of requirements analysis, especially as it relates to
> transaction-level modeling. I suggest we punt it to the VHDL-TC
> Requirements-SC.
> 
> Cheers,
> 
> PA
> 
> --
> Dr. Peter J. Ashenden         peter@ashenden.com.au
> Ashenden Designs Pty. Ltd.    www.ashenden.com.au
> PO Box 640                    VoIP: sip://0871270078@sip.internode.on.net
> Stirling, SA 5152             Phone (mobile):  +61 414 70 9106
> Australia
> 
> 
>> -----Original Message-----
>> From: owner-isac@server.eda.org 
>> [mailto:owner-isac@server.eda.org] On Behalf Of Chuck Swart
>> Sent: Friday, 2 February 2007 9:40 AM
>> To: isac@server.eda.org
>> Subject: ISAC: New IR 2109
>>
>>
>> This IR was just submitted. Let's discuss it at tonight's 
>> meeting. The IR is also in the eda.org data base.
>>
>> Chuck Swart
>>
>>
>>
>> -- 
>> This message has been scanned for viruses and
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>> believed to be clean.
>>
>>
> 
> 
> 


-- 
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SynthWorks Design Inc.           http://www.SynthWorks.com
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Received on Thu Feb 1 17:54:55 2007

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