ISAC: New IR 2119: Can't declare a protected type and object of that type in a single package

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VHDL Issue Number:        2119

Language_Version          VHDL-2002
Classification            LRM Examples, Notes and Appendices
Summary                   Can't declare a protected type and object of that type in a single package
Relevant_LRM_Sections     12.3.1.2 Type declarations
                          12.3.1.4 Object declarations
Related_Issues            
Key_Words_and_Phrases     protected body package shared variable
Authors_Name              Paul Butler
Authors_Phone_Number      512 683 8743
Authors_Fax_Number        
Authors_Email_Address     Paul.Butler@ni.com
Authors_Affiliation       National Instruments
Authors_Address1          11500 N. Mopac
Authors_Address2          Austin, TX 78759
Authors_Address3          

Current Status:           Submitted

Superseded By:

------------------------
Date Submitted:           28 June 2007
Date Analyzed:
Author of Analysis:
Revision Number:          0
Date Last Revised:

Description of Problem
----------------------

If a package contains a protected type declaration, the package body
contains the protected body declaration.  The elaboration rules seem
to disallow declaring a shared variable of the protected type in the
same package (the object elaboration includes elaborating its private
data, but that cannot happen prior to elaborating the protected body).
On the other hand, if I declare a protected type in an architecture
declarative region, the protected body appears in the same region.  In
this case, the elaboration rules appear to allow me to declare a
shared variable in the same region as the variable's type declaration.
The difference in these cases is subtle; it caught me off guard and
exposed a bug in my simulator.
    

Proposed Resolution
-------------------

I think declaring a type and objects of that type in the same package
is common.  If the restriction against shared variables in packages
cannot be relaxed (assuming this analysis is correct), at least add
some notes or example code in the LRM to point out the consequences of
the elaboration rules.

VASG-ISAC Analysis & Rationale
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TBD

VASG-ISAC Recommendation for IEEE Std 1076-2002
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TBD

VASG-ISAC Recommendation for Future Revisions
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TBD