ISAC: Proposed Agenda for ISAC meeting 10 October 2007 NOTE DAY CHANGE

Next Meeting Wednesday, October 10, 2007, 8 pm Pacific Daylight Time
             (Thursday, October 11, 2007, 3 am GMT)

Telecom info (same as always)
US 800-637-5822
Other +1 647-723-3937
Access Code 6850821

1. New ISAC Issues:

2122    Analyzed        Peter        Protected method has implied object 
parameter?
2123    Submitted                       Process resumption and callbacks
2124    Submitted                       Ordering of process execution 
and callbacks
2125    Submitted                       Resolved for std_ulogic is 
broken for '-'

2. Open ISAC Issues:

1070    ISAC-Approved                 VPI Issue 14 -- Prefixes in USE 
clauses
2099    Analyzed        Chuck           Alias declarations introduce 
homographs
2110    Submitted       Chuck           Implicit subtype conversions not 
defined
2119    Analyzed        Peter            Can't declare a protected type 
and object of that type in a single package
2120    Analyzed        Peter            How to access objects in higher 
level nested protected type
2121    Submitted                           Allow for vectors to have 
assigns and opens in the port map

3. Migration of pre-2002 IRs to Bugzilla:





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VHDL Issue Number:        2125

Language_Version          VHDL-2002
Classification            Language Definition Problem
Summary                   Resolved for std_ulogic is broken for '-'
Relevant_LRM_Sections     package std_logic_1164
Related_Issues            For Accellera 3.X revision, does "case?" depend on this behavior?  
    
Key_Words_and_Phrases     
Authors_Name              Jim Lewis
Authors_Phone_Number      503-590-4787
Authors_Fax_Number        
Authors_Email_Address     jim@synthworks.com
Authors_Affiliation       SynthWorks Design Inc.
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           Submitted

Superseded By:

------------------------
Date Submitted:           8 October 2007
Date Analyzed:
Author of Analysis:
Revision Number:          0
Date Last Revised:

Description of Problem
----------------------

When both a 'Z' and a '-' were driven on a signal the resolved value is currently 'X'.

Proposed Resolution
-------------------

For testbench modeling, it would be more useful if when both a 'Z' and
a '-' were driven on a signal that the resolved value would be '-'.
    
    I note that this is done for all other values UX01ZWLH, but not -
    
VASG-ISAC Analysis & Rationale
------------------------------
TBD

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD