Comment on IR2125

From: Peter Ashenden <peter_at_.....>
Date: Tue Oct 09 2007 - 17:49:46 PDT
Folks,

In IR2125, Jim suggests changing the resolution function in std_logic-1164
so that 'Z' and '-' resolve to '-' rather than 'X'.

To aid our discussion tomorrow, here's an excerpt from IEEE 1165-1993:

  A.8 Modeling with don't care's

  A.8.1 Use of the don't care state in synthesis models

  For synthesis, a VHDL program is a specification of the
  functionality of a design. VHDL can also be used to model (in order
  to simulate) real circuits. The former deals with logical function
  of the circuit, while the latter is concerned with function of a
  circuit from an electrical point of view. The nine-state logic type
  usage for synthesis is based on the assumption that the VHDL models
  will be logical function specifications and, therefore, attempts to
  restrict the usage of the logic type to logical function. The
  motivation for allowing the user to reference the values 'U' and 'X'
  (which do not specify the behavior of the circuit to be built, i.e.,
  one can not build a circuit which "drives an 'X'") is to allow such
  simulation artifacts to remain in models for synthesis for the sake
  of convenience. By having synthesis remove these references, the
  user is assuming only the kind of usage (of 'U' and 'X') that
  catches error states that should never occur in hardware.

  A.8.2 Semantics of '-'

  In designing the resolution function and the various logic tables in
  the package body, '-' is almost exclusively a syntactic shorthand
  for 'X', provided for compatibility with synthesis tools. This is
  evident from that fact that '-' becomes 'X' as soon as it is
  operated upon and when it is converted to subtype X01 or UX01. The
  "output don't care" value represents either a '1' or a '0' as the
  output of combinatorial circuitry, with respect to state encoding in
  particular.

In answer to Jim's question about the effect of his proposed change on the
case? statement: The expression in a case? must not be '-' (for a scalar) or
include a '-' element (for a vector). So propagating a '-' through a design
may cause more errors than would otherwise occur.

Cheers,

PA

--
Dr. Peter J. Ashenden         peter@ashenden.com.au
Ashenden Designs Pty. Ltd.    www.ashenden.com.au
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Received on Tue Oct 9 17:50:03 2007

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