Chuck, I am mostly happy with Peter's analysis. I find myself frequently referring to sequential and concurrent declarative regions, however, I will have to think about it as it may be limited to the topics Peter references and nothing else. Best, Jim > Chuck, > > This appeared to be such a no-brainer that I've done a first-cut analysis > (attached). If Jim's happy with it, we could perhaps deal with it by email > rather than having it sit until our next telecon. > > Cheers, > > PA > > -- > Dr. Peter J. Ashenden peter@ashenden.com.au > Ashenden Designs Pty. Ltd. www.ashenden.com.au > PO Box 640 VoIP: sip://0871270078@sip.internode.on.net > Stirling, SA 5152 Phone: +61 8 7127 0078 > Australia Mobile: +61 414 70 9106 > > >> -----Original Message----- >> From: owner-isac@server.eda.org >> [mailto:owner-isac@server.eda.org] On Behalf Of Chuck Swart - MTI >> Sent: Tuesday, 15 January 2008 06:05 >> To: isac@server.eda.org >> Subject: ISAC: new IR 2128 Shared Variable declarations in generate? >> >> >> This IR has also been copied to the website. >> Chuck Swart >> >> >> -- >> This message has been scanned for viruses and >> dangerous content by MailScanner, and is >> believed to be clean. >> >> > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Jan 14 17:12:51 2008
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